Ex Parte Yamamoto et al

Patent Trial and Appeal Board

Oct 10, 2017

14450801 (P.T.A.B. Oct. 10, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/450,801 08/04/2014 Tetsuro Yamamoto 880001-4079-US01 5231
134795 7590 10/12/2017
MICHAEL BEST & FRIEDRICH LLP (DC)
100 E WISCONSIN AVENUE
Suite 3300
MILWAUKEE, WI 53202
EXAMINER
SOTO LOPEZ, JOSE R
ART UNIT PAPER NUMBER
2694
NOTIFICATION DATE DELIVERY MODE
10/12/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
DCipdocket @ michaelbest. com
sbj ames @michaelbest.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TETSURO YAMAMOTO, KATSUHIDE UCHINO, and
MASAKAZU KATO1
Appeal 2016-004624
Application 14/450,801
Technology Center 2600
Before ROBERT E. NAPPI, JASON V. MORGAN, and JUSTIN BUSCH,
Administrative Patent Judges.
NAPPI, Administrative Patent Judge
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the
Examiner’s Final Rejection of claims 1 through 29. Oral arguments were
heard on September 19, 2017. A transcript of the hearing will be added to
the record in due course. We have jurisdiction over the pending claims
under 35 U.S.C. § 6(b).
We affirm-in-part.
1 According to Appellants, the real party in interest is Sony Corp. App.
Br. 3.
Appeal 2016-004624
Application 14/450,801
INVENTION
The invention is directed to display panel including: a pixel array
section in which electroluminescent display elements whose light emission
state is controlled by an active matrix driving system are arranged in a form
of a matrix; a first writing control line driving section and a second writing
control line driving section configured to drive each writing control line
from both sides of the pixel array section. See Abstract of Appellants’
Invention.
Claims 1 and 22 are illustrative of the invention and reproduced
below:
1. A display device comprising:
a plurality of pixel circuits arranged in a display area; and
driving circuitry configured to drive the pixel circuits,
each of the pixel circuits including a first sampling transistor,
drive transistor, a capacitor, a second sampling transistor and a
light emitting element,
the driving circuitry including write control circuitry configured
to control operation of the first sampling transistor and the second
sampling transistor,
wherein the driving circuitry is configured to drive the pixel
circuits by executing:
a first process to provide an offset potential through the second
sampling transistor to the capacitor during a first period;
a second process to provide a current through the drive
transistor to the capacitor at a beginning of a second period
and while the first sampling transistor is sampling an image
signal during the second period, the first process occurring
before the second process; a third process to provide a
driving current based on a voltage stored in the capacitor, to
the light emitting element via the drive transistor during a
third period, the second process occurring before the third
process,
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Application 14/450,801
wherein the second process begins when the first sampling
transistor transitions from an off state to an on state,
wherein a duration of the second period is defined by a period
in which the first sampling transistor is in the on state, and
wherein the write control circuitry includes a first write control
circuit and a second write control circuit that drive the pixel
circuits from both sides of the display area, the first and the second
write control circuits being connected to the first sampling
transistor and the second sampling transistor.
22. A display device comprising:
a plurality of pixel circuits arranged in a display area;
a plurality of signal lines extending in a first direction;
a plurality of scanning lines extending in a second direction, the
second direction being perpendicular to the first direction;
driving circuitry being configured to drive the pixel circuits,
each of the pixel circuits including:
a light emitting element;
a first transistor;
a capacitor configured to receive a voltage signal via the
first transistor; and
a second transistor configured to provide a driving
current for the light emitting element in response
to a voltage stored in the capacitor,
wherein the driving circuitry includes:
a scanning control circuit configured to control operation
of the first transistor, and
a power supply control circuit configured to control
power supply for the second transistor,
wherein the power supply control circuit includes a plurality of
buffer transistors each respectively connected to a power supply
control line, and wherein a direction of a channel length of each of
the buffer transistors is parallel to the first direction.
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Application 14/450,801
REJECTIONS AT ISSUE
The Examiner has rejected claims 6 and 7 under 35U.S.C. § 112
second paragraph as being indefinite. Final Action 6; Answer 2.2
The Examiner has rejected claims 1, 2, 5, and 6 under 35 U.S.C.
§ 102(b) as anticipated by Yamashita (US 2006/0170628). Final Action
7—9; Answer 3—5.
The Examiner has rejected claims 3,4, and 7 through 12 under
35 U.S.C. § 103 as unpatentable over Yamashita and Kimura (US
2001/0035849). Final Action 10—15; Answer 5—11.
The Examiner has rejected claims 13, 14, and 16 under 35 U.S.C.
§ 103 as unpatentable over Yamashita, Kimura, and Matsuda (US
6,552,768). Final Action 16—17; Answer 11—13.
The Examiner has rejected claims 17 through 19 and 21 under
35 U.S.C. § 103 as unpatentable over Yamashita, Kimura, Matsuda, and
Matsumoto (US 2007/0013629). Final Action 17—19; Answer 13—15.
The Examiner has rejected claim 20 under 35 U.S.C. § 103 as
unpatentable over Yamashita, Kimura, Matsuda, Matsumoto, and Imamura
(US 2006/0158095). Final Action 19-20; Answer 15—16.
The Examiner has rejected claims 22 and 24 under 35 U.S.C. § 103 as
unpatentable over Yamashita and Matsuda. Final Action 20-22; Answer
16-18.
2 Throughout this opinion we refer to the Appeal Brief, filed August 4,
2015; Reply Brief, filed March 30, 2016; Final Action mailed March 20,
2015, and the Examiner’s Answer, mailed on February 1, 2016.
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Application 14/450,801
The Examiner has rejected claim 23 under 35 U.S.C. § 103 as
unpatentable over Yamashita, Matsuda, and Yamazaki (US 2004/0256620).
Final Action 22—23; Answer 18—19.
The Examiner has rejected claims 25 through 27 and 29 under
35 U.S.C. § 103 as unpatentable over Yamashita, Matsuda, and Matsumoto.
Final Action 23—25; Answer 19—21.
The Examiner has rejected claim 28 under 35 U.S.C. § 103 as
unpatentable over Yamashita, Matsuda, Matsumoto, and Imamura. Final
Action 25—26; Answer 21—22.
ANALYSIS
We have reviewed Appellants’ arguments in the Briefs, the
Examiner’s rejection, and the Examiner’s response to the Appellants’
arguments. Initially, we note Appellants have not identified an error in the
Examiner’s rejection under 35 U.S.C. § 112, accordingly we summarily
sustain the Examiner’s rejection.3 Appellants’ arguments have persuaded us
of error in the Examiner’s rejection of claims 1, 2, 5, and 6 under 35 U.S.C.
§ 102 and claims 3, 4, 7 through 21, and 23 under 35 U.S.C. § 103.
Independent claims 1 and 8, and the claims which depend thereupon.
With respect to independent claims 1 and 8 the dispositive issue
presented by Appellants’ arguments is, did the Examiner err in finding
3 Appellants state, on page 15 of the Appeal Brief, that an After Final
amendment, dated June 1, 2015, renumbered claims 6 and 7 to new claims
35 and 36, and amended the claims to remedy the 112 rejection. The June 1,
2015, After Final Amendment was not entered. Thus, the 35USC§ 112
Footnote continued on next page.
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Yamashita teaches a process to provide current through the drive transistor
to the capacitor at a beginning of a second period and while the first
sampling transistor is sampling an image, where the second period begins
when the first sampling transistor transitions from an off state to an on state,
as recited in independent claim 1. Specifically, Appellants argue the
Examiner has shown that the current through the drive transistor to the
capacitor occurs during time T6 in Yamashita (see Fig 7), which is not the
time the sampling transistor transitions from an off state to an on state.
Reply Br. 8; App Br. 19—20. Rather, Appellants assert that the sampling
transistor transitions from the off state to an on state at time T5 (in figure 6).
Id. Thus, Appellants assert Yamashita does not teach the disputed
limitation.
In response to the Appellants’ arguments, the Examiner finds that
Yamashita’s time T5—T7, corresponds to the claimed second period and that
the claim is met because during this period the current through the drive
transistor to the capacitor occurs. Answer 24—26. We disagree with the
Examiner that this teaching meets the disputed limitation of claim 1.
Specifically, claim 1 recites the second period begins when the sampling
transistor transitions from the off state to an on state; there appears to be no
dispute that this occurs at Yamashita time T5. Claim 1 also states that the
process to provide current through the drive transistor to the capacitor occurs
“at the beginning of a second period.” There appears to be no dispute that
Yamashita teaches the process to provide current through the drive transistor
rejection of claims 6 and 7 is before us and Appellants have not alleged an
error in the rejection.
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to the capacitor occurs at time T6. We agree with the Appellants that the
subsequent actions which occur at time T6 are not at the beginning of the
period which begins at time T5. Accordingly, we will not sustain the
Examiner’s anticipation rejection of independent claim 1, and dependent
claim 2, 5, and 6.
The Examiner has not shown that the additional references used in the
rejections of dependent claims 3, 4, and 7 make up for the deficiencies in the
anticipation rejection. Accordingly, we similarly do not sustain the
rejections of claims 3, 4, and 7.
With respect to the obviousness rejection of independent claim 8,
Appellants assert the rejection is in error for the same reasons as claim 1.
Answer 26.
The Examiner’s response to Appellants’ arguments is similar to that
discussed above with respect to claim 1. Claim 8 is of slightly different
scope from claim 1. Claim 8 recites a process to provide current through the
drive transistor to the capacitor when (i.e., during, not after) the sampling
transistor transitions from an off state to an on state. Thus, we consider the
scope of claim 8 to require that the current is provided when the sampling
transistor is transitioning rather than at some point after the transition has
taken place. As discussed above, Yamashita provides current after (at time
T6) the sampling transistor transitions (at time T5). Accordingly, we do not
sustain the Examiner’s rejection of claim 8 and dependent claims 9 through
12 similarly rejected.
The Examiner has not shown that the additional references used in the
rejections of dependent claims 13 through 22 make up for the deficiencies in
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the anticipation rejection. Accordingly, we similarly do not sustain the
rejections of claims 13 through 22.
Independent claim 22 and the claims which depend thereupon.
Appellants argue that claim 22 recites: plural signal lines extending in
a in a first direction; plural scan lines extending in a second direction
perpendicular to the first direction; and a power supply control circuit which
includes plural buffer transistors each having a channel length parallel to the
first direction. App. Br. 39, Reply Br. 32. Appellants argue that the
Examiner relies upon Matsuda to teach the channel length of each buffer
transistor is parallel to the first direction, but that the rejection is in error as
Matsuda has no power supply control lines. App. Br. 38.
The Examiner’s rejection relies upon the combination of Yamashita
and Matsuda to teach the claim elements. Specifically, the Examiner finds
that Yamashita teaches the plural signal lines (SL Fig. 5) extend in a first
direction (horizontal) and plural scan lines (WS Fig. 5) extending in a
second direction (vertical) perpendicular to the first direction. Answer 16—
17, 34. Further, the Examiner relies upon Yamashita to teach a power
supply circuity item 5, which illustrates lines from the power supply (DS
Fig. 5) that are in the same direction (i.e., a second direction)as the scan
lines (WS Fig. 5). Answer 17. The Examiner finds that Matsuda teaches
control circuity (item 102, with horizontal output lines) which includes
plural buffer transistors in which the buffer has a channel length F (vertical)
which is parallel to the first direction. Answer 17, 34. We concur with the
Examiner, Matsuda teaches using control circuitry where the channel length
of the buffer transistors is perpendicular to the output lines (see Fig. 3, item
102, channel length F is perpendicular to the output line of the drive circuit)
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Application 14/450,801
and when combined with Yamashita’s power supply results in the channel
length in the first direction as claimed.
Appellants’ arguments in the Appeal Brief address the references
individually and not the combination. Appellants’ arguments in the Reply
Brief, do address the combination, by asserting that the combination does
not yield the claimed invention as:
[T]he transistor Tr4 and the drive scanner 5 of Yamashita is a current
source for the light-emitting element EL in Figure 5 of Yamashita, the
skilled artisan would have concluded that the shift register circuit 103
of Matsuda provides the video signals to the display pixel portion 108.
Being that the horizontal selector 3 in Figure 5 of Yamashita
also supplies video signals to the pixel array 1 (Yamashita at
paragraph [0033]), the skilled artisan would have further concluded
that horizontal selector 3 in Figure 5 of Yamashita performs a
function similar to the shift register circuit 103 of Matsuda.
Reply Br. 24. These arguments directed to claim 22 were presented for the
first time in the Reply Brief, and are merely attorney argument as they do
not identify evidence of record to support the assertions of what the skilled
artisan would have concluded. “Attorney’s argument in a brief cannot take
the place of evidence.” In re Pearson, 494 F.2d 1399, 1405 (CCPA 1974).
Bare attorney argument is insufficient to show the Examiner erred. Further,
Appellants have not shown good cause as to why these arguments could not
be presented earlier. As such, these arguments have not been considered,
and are waived. See Ex parte Borden, 93 USPQ2d 1473, 1476 (BPAI 2010)
(informative) (absent a showing of good cause, the Board is not required to
address arguments in Reply Brief that could have been presented in the
principal Appeal Brief); 37 C.F.R. § 41.41(b)(2) (2014). Thus, we sustain
the Examiner’s rejection of claim 22, and claim 24 grouped with claim 22.
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With respect to claim 23 Appellants argue the claim recites a channel
width for each buffer transistor is larger than the length of one pixel in a
direction of the signal line, a feature which is not taught by Yamashita,
Matsuda, or Yamazaki. App. Br. 40-41, Reply Br. 33—36.
The Examiner responds to Appellants’ arguments by stating that in
Figure 3 of Matsuda “the sum of distances L per pixel are about the same
size as the pixel itself’ but that Matsuda does not expressly state the channel
width is larger than the pixel as claimed. Answer 38—39. Further, the
Examiner finds that Yamazaki teaches, in paragraph 66, that the channel
width of a transistor is wider than its length and when this teaching is
coupled with Yamashita and Matsuda, the disputed limitation is taught.
Answer 39.
We disagree with the Examiner as we find insufficient evidence to
demonstrate that the combination of the references teaches channel width for
each buffer transistor is larger than the length of one pixel in a direction of
the signal line. Yamazaki, in paragraph 66, discusses a relationship between
the area of a driving transistor and the area of a pixel, but does not discuss
the relationship between the channel width of the transistor and the length of
the pixel. We do not find the other references disclose such a relationship
either. Accordingly, we do not sustain the Examiner’s rejection of claim 23.
With respect to claims 25 through 27 and 29, Appellants argue claim
25 recites three wirings, the first and the third wirings in a first layer and
formed of a first material and a second wiring in a second layer and formed
of a second material. App. Br. 42. Appellants argue that the Examiner
erroneously relies upon Matsumoto to teach the power control lines as
claimed. App. Br. 42— 44, Reply Br. 36, 26—27. Appellants reason that the
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skilled artisan would have construed Matsumoto’s teachings as directed to
something other than the drive scanner 5 in Yamashita and thus the
combination does not teach the power lines as claimed. App. Br 43 44.
We are not persuaded of error by these arguments. The Examiner has
provided a comprehensive response to Appellants’ arguments finding that
Matsumoto teaches the general concept of a driver with a bridge
configuration to route low voltage lines and high voltage lines in a manner
that prevents a short circuit and that it would be obvious to apply this
configuration to Yamashita. Answer 39, 40, 36. We concur with the
Examiner. Appellants’ argue that Matsumoto does not teach directly
incorporating the power lines into Yamashita’s circuit. We are not
persuaded by this reasoning. “The test for obviousness is not whether the
features of the secondary reference may be bodily incorporated into the
structure of the primary reference.... Rather, the test is what the combined
teachings of those references would have suggested to those of skill in the
art.” In re Keller, 642 F.2d 413, 425 (CCPA 1981); Accord In re Sneed 710
F.2d 1544 1550 (Fed Cir. 1983) (“[I]t is not necessary that the inventions of
the reference be physically combinable to render obvious the invention.”).
Further, Appellants’ assertions about what features of Matsumoto the skilled
artisan would have equated to features of Yamashita are just attorney
argument, and unsupported by any rationale or evidence to support the
assertions. As stated above bare attorney argument is insufficient to show
the Examiner erred. Accordingly, we are not persuaded of error in the
Examiner’s rejection of claim 25 and we sustain the rejection of claim 25
and claims 26, 27, and 29 grouped with claim 25.
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With respect to claim 28, Appellants argue that claim 28 is dependent
upon claim 25 and recites that the first material is Aluminum and the second
material is Molybdenum and that the combination of Yamashita, Kimura,
Matsuda, Matsumoto, and Imamura do not tech the use of the materials on
the three lines in the order claimed. App. Br 44-45, Reply Br. 37, 30—32.
The Examiner, in response to Appellants’ arguments, finds that
Matsumoto teaches making different lines out of different materials.
Answer 40, 37. Further, the Examiner finds that Imamura teaches power
lines can be made of four different materials, including Aluminum and
Molybdenum. Answer 37. The Examiner reasons that the skilled artisan
would chose two of the four materials listed in Imamura for the two
materials used in the lines of Matsumoto and that the selection of Aluminum
and Molybdenum is one of a finite number of options. Thus, the Examiner
considers the limitation to be obvious. We concur with the Examiner and
consider the Examiner to have presented sufficient evidence to demonstrate
the limitation of claim 28 is obvious. “When there is a design need or
market pressure to solve a problem and there are a finite number of
identified, predictable solutions, a person of ordinary skill in the art has good
reason to pursue the known options within his or her technical grasp. If this
leads to the anticipated success it is likely the product is not of innovation
but of ordinary skill and comment sense” KSR Int 7 Co. v. Teleflex Inc., 550
U.S. 398, 421 (2007). Accordingly, we sustain the Examiner’s rejection of
claim 28.
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DECISION
The decision of the Examiner to reject claims 6 and 7 under
35 U.S.C. § 112 is affirmed.
The decision of the Examiner to reject claims 1, 2, 5, and 6 under
35 U.S.C. § 102 and to reject claims 3, 4, 7, through 21 and 23 under
35 U.S.C. § 103 is reversed.
The decision of the Examiner to reject claims 22 and 24 through 29
under 35 U.S.C. § 103 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED-IN-PART
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