Ex Parte Yamaguchi et al

Patent Trial and Appeal Board

Jun 28, 2013

10260724 (P.T.A.B. Jun. 28, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte TAKAHIRO YAMAGUCHI, MASAHIRO ISHIDA and
MANI SOMA
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Appeal 2010-012033
Application 10/260,724
Technology Center 2600
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Before ELENI MANTIS MERCADER, KRISTEN L. DROESCH and
CATHERINE SHIANG, Administrative Patent Judges.

DROESCH, Administrative Patent Judge.
DECISION ON APPEAL

Appeal 2010-012033
Application 10/260,724

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STATEMENT OF THE CASE
The Appellants seek review under 35 U.S.C. § 134(a) of a final
rejection of claims 1-19. We have jurisdiction under 35 U.S.C. § 6(b). We
REVERSE.
BACKGROUND
The Appellants’ disclosed invention relates to a jitter measurement
apparatus and method for measuring a jitter of a signal under measurement.
The apparatus includes a delay circuit which generates a signal that is
delayed from the signal under measurement by a predetermined delay time,
and a phase detector which detects an instantaneous phase error between the
signal under measurement and the delayed signal. Abs.; Spec. 4.
Claim 1 is illustrative and is reproduced below (disputed limitation in
italics):
1. A jitter measurement apparatus for measuring a jitter of a signal
under measurement, comprising:
a delay circuit operable to generate a delayed signal that is
delayed from said signal under measurement by a
predetermined delay time, the predetermined delay time
being unchanged during the measuring of the jitter of the
signal under measurement; and
a phase detector outputting a pulse signal representing an
instantaneous phase error which is detected as a
fluctuation of a time interval between an edge of said
signal under measurement and an edge of said delayed
signal, said pulse signal having a pulse width
corresponding to said time interval,
wherein the jitter of said signal under measurement is
measured using said pulse signal.

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Application 10/260,724

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Rejections
Claims 1, 2, 5, 12, 14-17 and 19 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Yongsam Moon et al., An All-analog
Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range
Operation and Low-Jitter Performance, IEEE Journal of Solid State
Circuits, vol. 35, no. 3, pp. 3770384, March 2000 (“Moon”).
Claims 3, 4, 6-11, 13 and 18 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Moon and Takahiro J. Yamaguchi, et al.,
Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic
Signal Method, Proceedings of 18
th
IEEE VLSI Test Symposium 2000, pp.
395-402 (“Yamaguchi”).
ISSUE
Did the Examiner err in finding that Moon teaches or suggests “the
predetermined delay time being unchanged during the measuring of the jitter
of the signal under measurement,” as recited in claim 1, and similarly recited
in independent claims 17 and 19?
ANALYSIS
We have reviewed the Examiner’s rejection in light of the Appellants’
arguments in the Appeal Brief presented in response to the Final Office
Action. We agree with the Appellants’ conclusions. We highlight and
address specific findings and arguments for emphasis as follows.
The Examiner directs attention to Moon’s description of ICLK and
QCLK on page 379 and shown in Figure 4, reproduced below, and finds that
Moon describes the disputed claim limitations. Ans. 4-5, 8-9.

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Figure 4 of Moon is below:

Figure 4 depicts a configuration of a replica delay line.
The Examiner offers additional clarification of the Office’s position and
asserts that the control voltage VCR is generated after measuring the jitter, is
fed back for the next measurement, and is used to control the delay of the
subsequent signal. Ans. 9. The Examiner further directs attention to Moon’s
description that “QCLK is delayed from ref-CLK by one delay cell” and
asserts that this description clearly states that the predetermined delay is one
unit delay and is unchanged during measurement of the jitter of signal under
measurement. Id. The Examiner further finds: 1) the delay is predetermined
because the delay is determined before the next jitter measurement; and 2)
the predetermined delay is unchanged because Moon does not teach that the
delay is changed during the measurement of the jitter. Ans. 9.
The Appellants assert that in Moon, the replica delay line generates a
control voltage VCR which controls both the delay elements in the core DLL
(delay-locked loop) and the single delay cell in the replica delay line. Br. 11;
see also Moon’s Figure 3 reproduced below which depicts the replica delay
line from Figure 4 together with the core DLL.

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Figure 3 of Moon is below:

Figure 3 depicts a block diagram of analog DLL.
The Appellants argue that the delay amount of the single delay cell varies
dynamically according to the voltage VCR and in order for the DLL circuit to
work properly, the single delay cell should accept the feedback voltage VCR
and adjust dynamically at all times. Id. The Appellants also direct attention
to Moon’s Figure 5 (b) reproduced below, as showing how changes in the
control voltage VCR, denoted as Vd, affect the delay difference TRDC
between the ICLK and QCLK signals. Br. 11.
Moon’s Figure 5b is reproduced below.

Figure 5b depicts the gain curve for
the CSPD (current steering phase detector).
The Appellants further direct attention to Moon’s description that TRDC will
eventually settle at 1/4 , which represents 1/8 x TCLK, where TCLK is the
period of the reference clock. Br. 11 (citing Moon p. 379, paragraph 6). On
this basis, the Appellants argue that eventually settling to a value is

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completely different than the “predetermined delay time” required by the
claims. Id. In other words, the Appellants argue that eventually settling to a
value of 1/8 x TCLK is completely different than the predetermined delay
time being unchanged during the measuring of the jitter of the signal under
measurement.
We agree with Appellants’ arguments that the delay amount of the
single delay cell varies dynamically according to the voltage VCR. The
Appellants argument is supported by: 1) the variation in VCR shown in the
graphical portion of Moon’s Figure 4; 2) the description of VCR as shared by
the replica delay cell and the core DLL (Moon p. 379, col. 1, last ¶); 3) the
description that due to sharing of VCR, the delay time (TRDC) of the replica
delay cell is almost equal to the delay time (TDC) of each delay cell in the
core DLL, but are not exactly the same unless VCR equals bias (id.); and 4)
the description referring to Figure 5(b) above that if TRDC is smaller than 1/8
x TCLK, the change of VCR, denoted as Vd, will become negative and TRDC
will increase (arrow pointing to the right) and if TRDC is between 1/8 x TCLK
and 7/8 x TCLK, Vd will be positive and TRDC will decrease (arrows pointing
to the left) (Moon p. 379, col. 2, last ¶). While we agree with the Examiner
that the control voltage VCR is fed back for the next measurement and is used
to control the delay of the subsequent signal, we also appreciate that the
control voltage VCR for the immediately preceding measured signal is fed to
the replica delay cell for the currently measured signal. The only instance of
time when the control voltage VCR is unavailable to be fed back to the
replica delay cell to affect the delay time (TRDC) may be for the very first
instance of measuring the reference clock signal (Ref-CLK). Accordingly,

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we are unable to agree with the Examiner that the predetermined delay is
unchanged during the measurement of the jitter of the signal under
measurement.
For these reasons, Moon does not provide sufficient factual support
for the Examiner’s findings and conclusion of obviousness. Accordingly, we
do not sustain the rejection of claims 1, 2, 5, 12, 14-17 and 19 as obvious
over Moon. As applied by the Examiner, Yamaguchi does not remedy the
deficiencies of Moon. Ans. 6. Therefore, for the same reasons, we do not
sustain the rejection of dependent claims 3, 4, 6-11, 13 and 18 as obvious
over Moon and Yamaguchi.
DECISION
We REVERSE the rejection of claims 1-19 under 35 U.S.C. § 103(a)
as unpatentable over the prior art.
REVERSED

ELD