Ex Parte Woyzichovski

Board of Patent Appeals and Interferences

Aug 28, 2012

10501310 (B.P.A.I. Aug. 28, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/501,310 11/23/2004 Roman Woyzichovski 10901/81 6114
26646 7590 08/29/2012
KENYON & KENYON LLP
ONE BROADWAY
NEW YORK, NY 10004
EXAMINER
BOCURE, TESFALDET
ART UNIT PAPER NUMBER
2611
MAIL DATE DELIVERY MODE
08/29/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte ROMAN WOYZICHOVSKI
____________

Appeal 2010-002810
Application 10/501,310
Technology Center 2600
____________

Before JEFFREY S. SMITH, BRUCE R. WINSOR, and
ANDREW CALDWELL, Administrative Patent Judges.

SMITH, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2010-002810
Application 10/501,310

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STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 21-42, which are all the claims remaining in the
application. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

Representative Claim
21. A method for interpolating at least two position-dependent,
periodic analog signals that are phase-shifted with respect to one another and
which are generated by scanning a measuring scale, comprising:
converting each of the analog signals into a digital data stream by a
sigma-delta modulator;
generating a string of results by combining the data streams with
correctional values and subsequently combining the data streams with one
another;
generating from the string of results (a) new correctional values in
accordance with a quality criterion that is to be satisfied during interpolation
and (b) output signals of the interpolation;
accumulating over a specifiable time interval values of the string of
results for generating the correctional values and the output signals; and
using a signal sequence generated by the accumulation as an address
sequence for generating the correctional values and for generating the output
signal.

Prior Art
Liessner US 5,079,549 Jan. 7, 1992
Garverick US 5,134,578 July 28, 1992
Khan US 2002/0116181 A1 Aug. 22, 2002

Examiner’s Rejections
Claims 21-24, 26, 27, and 30-42 stand rejected under 35 U.S.C. §
103(a) as being unpatentable over Liessner and Garverick.
Appeal 2010-002810
Application 10/501,310

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Claim 25 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Liessner, Garverick, and Applicant’s admitted prior art.
Claims 28 and 29 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Liessner, Garverick, and Khan.

ANALYSIS
Appellant contends that the structure taught by Liessner is analog
rather than digital. App. Br. 6. The Examiner finds that converting
Liessner’s structure from analog to digital would have been obvious. Ans.
4-5. The Examiner finds that the analog functions of detector 22, multi-step
mode detector 23, count generator 24, and up/down counter 26 would
remain analog, and the multipliers 12, 14 and adder 20 would be redesigned
as digital circuits to prevent signal loss. Ans. 10-11. Appellant contends
that adding an analog to digital converter to the input of the system, then
adding a digital to analog converter to the output of adder 20 would increase,
rather than prevent, signal loss.
The Examiner finds that digital implementations provide for zero loss
as is notoriously known and understood in the art. Ans. 10. However, the
Examiner has not identified objective evidence to establish that the data
integrity gained by replacing Liessner’s analog multipliers and adder with
digital circuits would outweigh the losses introduced by changing the output
of the adder from a digital to an analog signal.
We decline to speculate on the amount of loss caused by converting a
signal from digital to analog. We also decline to speculate on the amount of
increase in data integrity caused by replacing analog circuits with digital
circuits. This specific fact finding is better left to the Examiner. Given that
Appeal 2010-002810
Application 10/501,310

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this specific fact finding is not presented to us in the record before us, we do
not sustain the rejection of independent claims 21 and 40-42, or dependent
claims 22-39, under 35 U.S.C. § 103.

DECISION
The rejection of claims 21-24, 26, 27, and 30-42 under 35 U.S.C. §
103(a) as being unpatentable over Liessner and Garverick is reversed.
The rejection of claim 25 under 35 U.S.C. § 103(a) as being
unpatentable over Liessner, Garverick, and Applicant’s admitted prior art is
reversed.
The rejection of claims 28 and 29 under 35 U.S.C. § 103(a) as being
unpatentable over Liessner, Garverick, and Khan is reversed.

REVERSED

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