Ex Parte WILSON et al

Patent Trial and Appeal Board

Feb 7, 2019

14667229 (P.T.A.B. Feb. 7, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/667,229 03/24/2015
23125 7590 02/11/2019
NXP USA, Inc.
LAW DEPARTMENT
6501 William Cannon Drive West TX30/0E62
AUSTIN, TX 78735
FIRST NAMED INVENTOR
PETER J. WILSON
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
MT13127NH 3464
EXAMINER
HUISMAN, DAVID J
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
02/11/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip.department.us@nxp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PETER J. WILSON and BRIAN C. KAHNE
Appeal2018-006367
Application 14/667 ,229
Technology Center 2100
Before JOSEPH L. DIXON, JAMES W. DEJMEK, and
STEPHEN E. BELISLE, Administrative Patent Judges.
DIXON, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2018-006367
Application 14/667,229
STATEMENT OF THE CASE
Appellants 1 appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b ).
We affirm.
The claims are directed to computer systems and methods for context
switching. Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A data processing system comprising:
a plurality of contexts, wherein each context includes a
corresponding register file and a corresponding instruction
buffer;
a current context indicator configured to indicate a context
of the plurality of contexts as a current context;
an instruction queue configured to store fetched
instructions for execution using the current context; and
a scheduler circuit coupled to a context selector and
configured to, in response to a context switch event, save a
current context instruction state from the instruction queue to the
corresponding instruction buff er of the current context, select a
next context of the plurality of contexts, restore a context
instruction state directly from the corresponding instruction
buffer of the next context to the instruction queue, and set the
current context indicator to indicate the selected next context as
the current context.
1 Appellants indicate that NXP USA, Inc. is the real party in interest. (App.
Br. 3.)
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Application 14/667,229
REFERENCE
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Eickemeyer US 2005/0114856 Al May 26, 2005
REJECTIONS
The Examiner made the following rejections:
Claims 1, 2, 6, 8, 10, 11, and 15-19 are rejected under 35 U.S.C.
§ 102( a)( 1) as being anticipated by Eickemeyer.
Claims 3-5, 7, 9, 12-14, and 20 are rejected under 35 U.S.C. § 103 as
being unpatentable over Eickemeyer in view of the Examiner's taking of
Official Notice.
ANALYSIS
The Examiner identifies that the abbreviated rejections in the
prosecution history were due to the application being under the "first action
interview pilot." (Ans. 3). (See Request filed March 24, 2015). In the First
Office Action the Examiner cited Eickemeyer figures 2-7 and their
corresponding disclosure along with the "background," which includes
paragraphs 2-9 and, specifically, column 1, lines 40-41, which discusses
two sets of general purpose registers that are provided and two sets of
instruction buffers that are provided.
The level of detail of the First Office Action appears to be
commensurate with the level of detail on the associated forms. Appellants
requested the abbreviated office action and then waived the associated
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Application 14/667,229
interview to discuss the abbreviated factual findings. (Response April 24,
2017, page 2).
We find the prosecution on the merits in the present appeal has
provided Appellants with the requisite notice based upon Appellants'
election to participate in an abbreviated prosecution, which allowed
abbreviated factual findings which Appellants did not appreciate the level of
detail therein. Appellants subsequently proceeded to appeal on a less than
fully developed record.
Anticipation
With respect to independent claims 1, 10, and 15, Appellants argue
that the Eickemeyer reference swaps the contents of the primary instruction
buffer with the backup instruction buffer when a primary thread stalls.
(App. Br. 11-12). Appellants contend that claim 1 requires
a context instruction state from the corresponding instruction
buffer of the next context is restored directly to the instruction
queue in response to a context switch event. Claim 1 does not
swap the contents of a primary and a backup buff er before
providing the context state from the primary buff er to the
instruction queue as in Eickemeyer. Rather, claim 1 restores a
context instruction state directly from the instruction buffer of
the next context to the instruction queue; there is no swapping of
buffer contents in claim 1 to get the context instruction state of
the next context to the instruction queue as in Eickemeyer.
(Eickemeyer, paragraphs [0022] and [0023]).
(App. Br. 12) (emphasis omitted). Appellants further argue that "Appellant
respectfully submits that different elements in Eickemeyer need to be
identified for corresponding different elements of claim 1, and this alone
indicates that Eickemeyer does not teach all the elements of claim 1." (App.
Br. 13).
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Appellants further contend:
It is important to note that claim 1 requires an instruction
queue, an instruction buffer for a current context, and an
instruction buffer for a next context, and that there is no
swapping of context states between the instructions buffers
before the context instruction state is provided to the instruction
queue as there is in Eickemeyer. In claim 1, the context
instruction state is provided directly to the instruction queue from
the instruction buffer of the next context. This is not taught or
suggested by Eickemeyer as in Eickemeyer, the contents of the
backup buffer 214 (next context) is swapped with the primary
buffer 212, and the context in the primary buffer is then
transferred to the instruction queue 150. (Eickemeyer, FIGs. 1
and 2, and paragraphs [0007], [0022] and [0023]). Claim 1 is
distinguishable from Eickemeyer for at least these reasons.
(App. Br. 13). Appellants further argue that the Examiner's broadest
reasonable interpretation does not mean the "broadest possible
interpretation" (App. Br. 14) (emphasis omitted). Appellants contend that
"While Eickemeyer shows primary and backup instruction buffers for each
context, each context in Eickemeyer does not includes its own register."
(App. Br. 15). Appellants identify that the incorporated by reference US
patent application 10/682, 134 (Luick reference) (see Eickemeyer ,r 1) "is
cited as a preferred arrangement for a register file to be used in connection
with the primary and backup instruction buffers taught in Eickemeyer," but
the Eickemeyer reference uses the same register for switching between
contexts, not a corresponding register file for each context. (App. Br. 15-
16).
In the Final Action, the Examiner clarifies the mapping of the
Eickemeyer reference to the claim limitations, and the Examiner finds
Appellants' argument unpersuasive
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Application 14/667,229
because a primary buffer is an instruction queue that buffers
instructions in order (Io to IN). Thus, in FIG. 2 for example, when
there is a thread switch, the next context instruction state from
backup buff er 214 is restored to instruction queue 212. The
examiner notes that the addition of "directly" to the independent
claims does not overcome the rejection because instructions are
moved from buffer 214 directly to queue 212.
(Final Act. 5). We agree with the Examiner that the Appellants' arguments
with regards to "directly to the instruction queue" are unpersuasive because
the Examiner finds that Appellants are not arguing the rejection as applied
by the Examiner, and the Examiner further clarifies the mapping of the claim
limitations to the Eickemeyer reference, that the instruction state is restored
from buffer 214 directly to queue 212, where primary buffer 212 is a queue
that buffers instructions in order as they wait to be selected for transmission
to logic 150. (Ans. 4). The Examiner finds:
Eickemeyer has taught a queue 212 and a buffer 214 for current
and next contexts. The[] claims do not require a separate
instruction buffer for each context. Buffer 214, which is shared
by the current and next contexts selectable by selector 130, is an
instruction buffer that corresponds to each of these contexts (i.e.,
each of these contexts is stored in buffer 214 when stalled).
Queue 212 is the buffer for storing instructions of the current
context. Further, even though appellant argues that swapping
occurs in Eickemeyer but doesn't occur in the claimed invention,
the examiner notes that the claims are open-ended and do not
exclude any such swapping.
(Ans. 5).
We agree with the Examiner that the claims are open-ended and do
not exclude any such swapping. 2
2 We note that Appellants have not identified any specific disclosure for the
claim phrase "directly" for the corresponding instruction buffer and only
provided a general citation for the complete claim. ("See, e.g., Appellant's
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In response to the Examiner's clarification of the rejection in the
Examiner's Answer, that the claims do not require "a separate instruction
buffer for each context," Appellants repeat the language of the claim and
emphasize the word "and" ("there are a plurality of contexts, wherein each
context includes a corresponding register file (310) and a corresponding
instruction buffer (308)."). (Reply Br. 2). Appellants further argue:
Eickemeyer does not teach or suggest a register file and an
instruction buffer for each context or "restore a context
instruction state directly from the corresponding instruction
buffer of the next context to the instruction queue" as recited in
claims 1 and 10, or "restoring a context instruction state directly
to the instruction pipeline from the corresponding instruction
buff er of the next context" as recited in claim 15.
(Reply Br. 2). Additionally, Appellants contend that the Examiner's reliance
upon the incorporated by reference material from the Luick US Patent No.
7,743,237 (parent application) is incorrect. Appellants contend that the
Luick reference instead discloses one register file in which different bits are
used to indicate which thread is executing. (Reply Br. 2).
The Examiner finds:
the parent application [Luick ] very clearly sets forth a register
file containing one set of registers (register file) for each
thread/context (e.g. page 4, lines 5-15) .... Alternatively, from
page 5, lines 9-15, of the parent application [Luick ], there may
be just two register files/sets for four threads, but even still, each
context/thread has a corresponding register file. Further, even if
there were just one register file, the claims are broad enough to
include just one register file that corresponds to all contexts.
Specification at paragraphs [0010]-[0025] and FIGS. 2, 3, AND 4)." (App.
Br. 8.)
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(Ans. 6). We agree with the Examiner and find Appellants' arguments do
not show error in the Examiner's finding of anticipation of the claims by the
Eickemeyer reference with the incorporated subject matter from the Luick
reference. As a result, we agree with the Examiner the Eickemeyer reference
discloses (with its incorporated subject matter) "a plurality of contexts,
wherein each context includes a corresponding register file and a
corresponding instruction buff er" and "restore a context instruction state
directly from the corresponding instruction buffer of the next context to the
instruction queue" as explained by the Examiner. 3 As a result, Appellants
have not shown error in the Examiner's finding of anticipation of
independent claim 1.
With respect to independent claims 10 and 15, Appellants rely upon
the arguments advanced with respect to independent claim 1 and merely
identify the corresponding claim language and contend the Eickemeyer
swaps the contents of a primary buffer and a backup buffer whereas claim 10
sends the new context directly to the instruction pipeline when a context
switch event occurs. (App. Br. 13-14).
With respect to dependent claims 2-7, 9, 11-13, and 16-20,
Appellants do not set forth separate arguments for patentability and rely
upon the arguments set forth with respect to independent claim 1. But with
regards to dependent claims 8 and 14, Appellants further argue Eickemeyer
3 Additionally, we note that Appellants' Summary of the Claimed Subject
Matter does not expressly identify any corresponding location or support for
the claim limitation "directly to the instruction queue." We leave it to the
Examiner to further evaluate this issue in any further prosecution on the
merits.
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fails to disclose that each context of the plurality of contexts also includes
context scheduling information (in addition to a corresponding register file
and corresponding instruction buffer), as recited in dependent claims 8 and
14. (App. Br. 16-17).
With regards to dependent claims 8 and 14, the Examiner finds
Appellants' argument unavailing because
First, appellant merely asserts, but provides no reasoning. The
examiner notes that "context scheduling information" is very
broad and could encompass any information involved in
scheduling in some way. FIG. 2 at the very least shows
instructions (IO to IN), which are scheduled for execution. Thus,
the instructions are scheduling information. Further, as is known,
instructions include sources and destinations which are taken
into account when scheduling. Thus, these source/ destination
identifiers are also scheduling information. Inherent program
counters for the contexts would also be scheduling information
as these indicate which instructions are to be fetched and
eventually scheduled. These are just examples of things that
could map to "context scheduling information".
(Ans. 6-7).
We agree with the Examiner that Appellants have not provided a
specific argument for patentability, but merely repeat the language of the
claim. Further, we find the Examiner has provided a reasoned explanation
of the claim interpretation and how prior art discloses claimed invention.
(Ans. 6-7).
Appellants do not specifically respond to the Examiner's clarifications
in the Reply Brief regarding claims 8 and 14. As a result, Appellants have
not shown error in the Examiner's finding of anticipation of claims 8 and 14.
Obviousness
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Appellants rely upon the arguments advanced with respect to
independent claim 1. (App. Br. 17).
Because we find no error in the Examiner's anticipation rejection, we
similarly find Appellants' arguments unpersuasive with regards to the
obviousness rejection.
CONCLUSIONS
The Examiner did not err in rejecting claims 1, 2, 6, 8, 10, 11, and 15-
19 based upon anticipation under 35 U.S.C. §102, and the Examiner did not
err in rejecting claims 3-5, 7, 9, 12-14, and 20 based upon obviousness
under 35 U.S.C. § 103.
DECISION
For the above reasons, we affirm the Examiner's anticipation rejection
of claims 1, 2, 6, 8, 10, 11, and 15-19, and we affirm the Examiner's
obviousness rejection of claims 3-5, 7, 9, 12-14, and 20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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