Ex Parte Watts

Board of Patent Appeals and Interferences

Sep 16, 2010

11137032 (B.P.A.I. Sep. 16, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte LA VAUGHN WATTS JR.
____________

Appeal 2009-008260
Application 11/137,032
Technology Center 2100
____________

Before JOHN A. JEFFERY, JOSEPH L. DIXON, and JAMES R. HUGHES,
Administrative Patent Judges.

DIXON, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

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The Appellant appeals under 35 U.S.C. § 134(a) from a non-final
rejection of claims 24-47. Claims 1-23 have been canceled. We have
jurisdiction under 35 U.S.C. § 6(b).
We Affirm.
I. STATEMENT OF THE CASE
The Invention
The invention at issue on appeal relates to a method and apparatus for
managing the temperature and the power of a central processing unit (CPU)
by changing the clock time of the CPU based on the real-time temperature
and the activity-level within of the CPU of a portable computer (Spec. 1).

The Illustrative Claims
Claims 24, 35, and 44, illustrative claims, reads as follows:
24. A method, comprising the steps of:
determining temperature and a work load level associated with
a processor; and
using results of said determining for reducing power
consumption associated with said processor as said work load
level decreases.
35. A method, comprising the steps of:
determining temperature and a work load level associated with
a processor; and
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using results of said determining for increasing power
consumption associated with said processor as said work load
level increases.
44. A method, comprising the steps of:

determining temperature and a work load level associated with
a processor; and
using results of said determining for reducing power
consumption associated with said processor as said work load
level decreases (and as said work load level increases)2 and said
temperature is at and or above a reference temperature and
increasing power consumption associated with said processor as
said work load level increases and said temperature is below
said reference temperature.
The References
The Examiner relies on the following references as evidence:
Sheets US 4,670,837 Jun. 2, 1987
Fairbanks US 5,021,679 Jun. 4, 1991
Thomas US 5,752,011 May 12, 1998

The Rejections
The following rejections are before us for review:
Claims 24-47 stand provisionally rejected under non-statutory
non-obviousness-type double patenting as being unpatentable over the
claims 22-44 of co-pending Application No. 11/123,464 in view of

2 The language in the parenthesis seems to be a typographical error.
However, one ordinary skill in the art would still understand the meaning of
the claim language.
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Thomas.
Claims 24-47 stand provisionally rejected under non-statutory
non-obviousness-type double patenting as being unpatentable over
claims 24-49 of co-pending Application No. 11/137,007.
Claims 30, 32, and 41 stand rejected under 35 U.S.C. § 112 first
paragraph as failing to comply with the written description requirement3.
Claims 24-34 and 45 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Sheets in view of Thomas.
Claims 35, 42-44, and 46-47 stand rejected under 35 U.S.C. §
103(a) as being unpatentable over Fairbanks in view of Thomas.
Claims 36-41 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Sheets, Fairbanks, and Thomas.
Only those arguments actually made by the Appellant have been
considered in this decision. Arguments which the Appellant could have
made but chose not to make in the Briefs have not been considered and are
deemed to be waived. See 37 C.F.R. § 41.37 (c)(1)(vii) (2008).

3 The Examiner withdrew the rejection of claims 26 and 37 under 35 U.S.C.
§ 112 1st paragraph (Ans. 11).
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II. ISSUES
1. Has the Examiner erred in identifying that claims 24-47
stand rejected under provisional nonstatutory obviousness-type double
patenting as being unpatentable over claims 22-44 of co-pending
Application No. 11/123,464 in view of Thomas?
2. Has the Examiner erred in identifying that claims 24-47 stand
rejected under provisional nonstatutory obviousness-type double patenting
as being unpatentable over claims 24-49 of co-pending Application No.
11/137,007?
3. Has the Examiner erred in finding that claims 30, 32, and
41 fail to comply with the written description requirement under 35
U.S.C. § 112, first paragraph, in particular whether the clock frequency
and speed lowered in incremental steps claimed in claims 30 and 32,
and whether the power consumption is accomplished while the
processor is processing data claimed in claim 42, have written
description support in the Specification in such a way as to reasonably
convey to a skilled artisan that the Appellant had possession the claimed
invention as of the filing date?
4. Has the Examiner erred in identifying that the combination of
Sheets and Thomas teaches and fairly suggests “determining temperature
and a work load level associated with a processor; and using results of said
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determining for reducing power consumption associated with said processor
as said work load level decreases” as recited in claims 24 and 45?
5. Has the Examiner erred in identifying that the combination of
Fairbanks and Thomas teaches and fairly suggests the limitations “using
results of said determining for increasing power consumption associated
with said processor as said work load level increases” as recited in claim 35
and “using results of said determining for reducing power consumption
associated with said processor as said work load level decreases and as said
work load level increases temperature is at and or above a reference
temperature and increasing power consumption associated with said
processor as said work load level increases and said temperature is below
said reference temperature” as recited in claims 44 and 47?
6. Has the Examiner erred in identifying that the combination of
Sheets, Fairbanks, and Thomas teaches and fairly suggests claimed
limitations as recited in claims 36-41, in particular, “an amount of said
increasing power consumption is proportional to the increase of said work
load level”, recited in claim 36, and “said increasing power consumption
continues until one of: a) no increase in work load level is detected over a
previous determination of work load level; b) said processor has reached its
maximum power consumption level; and c) said temperature is at and/or
above a reference temperature” recited in claims 38-39?
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III. PRINCIPLES OF LAW
Nonstatutory Obviousness-type Double Patenting

A nonstatutory obviousness-type double patenting rejection is
appropriate where the conflicting claims are not identical, but at least one
examined application claim is not patentably distinct from the reference
claim(s) because the examined application claim is either anticipated by, or
would have been obvious over, the reference claim(s). See e.g., In re Berg,
140 F.3d 1428 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046 (Fed. Cir.
1993); In re Longi, 759 F.2d 887 (Fed. Cir. 1985).

Written Description Requirement
The test for determining compliance with the written
description requirement is whether the disclosure of the
application as originally filed reasonably conveys to the artisan
that the inventor had possession at that time of the later claimed
subject matter, rather than the presence or absence of literal
support in the specification for the claim language.

In re Kaslow, 707 F.2d 1366, 1375 (Fed. Cir. 1983) (citations omitted).
The term “possession,” however, has never been very
enlightening. It implies that as long as one can produce records
documenting a written description of a claimed invention, one
can show possession. But the hallmark of written description is
disclosure. Thus, “possession as shown in the disclosure” is a
more complete formulation. Yet whatever the specific
articulation, the test requires an objective inquiry into the four
corners of the specification from the perspective of a person of
ordinary skill in the art. Based on that inquiry, the specification
must describe an invention understandable to that skilled artisan
and show that the inventor actually invented the invention
claimed.
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Ariad Pharmaceuticals, Inc. v Eli Lilly & Com. 598 F.3d 1336, 1351 (Fed
Cir. 2010) (en banc).
Obviousness
“Obviousness is a question of law based on underlying findings of
fact.” In re Kubin, 561 F.3d 1351, 1355 (Fed. Cir. 2009). The underlying
factual inquiries are: (1) the scope and content of the prior art, (2) the
differences between the prior art and the claims at issue, (3) the level of
ordinary skill in the pertinent art, and (4) secondary considerations of
nonobviousness. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007).

IV. FINDINGS OF FACT
The following findings of fact (FFs) are supported by a preponderance
of the evidence.
Thomas
1. Thomas discloses that a temperature sensor produces a
temperature based on the temperature of a processor that operates on plural
clock frequencies. The frequency of the clock supplied to the processor is
varied depending on the temperature of the processor (col. 2, ll. 43-65).
2. Thomas further discloses an embodiment of setting the clock
frequency according to the determined temperature:
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Note that when no activity is detected by the activity detector
48, then the sleep clock is output. However, when activity is
detected, then the normal clock is output if the chip temperature
is “hot” and the fast clock is output if the chip temperature is
not “hot”. Like previous embodiments, this embodiment
prevents overheating and conserves energy.
(col. 7, ll. 51-57) (Emphasis added).
Sheets
3. Sheets discloses that a method and microprocessor-based
system for conserving power by adjusting the operating clock frequency
upon determining the processing load:
The magnitude of power consumed by a MOS device at a given
voltage is substantially directly proportional to the frequency at
which the device is operated. In the case of microprocessor 101,
which is a relatively complex MOS device, the duration of each
execution cycle is defined by the signal received at a CLK
terminal. In accordance with the present exemplary
embodiment of the invention, a digital, voltage-controlled
oscillator (VCO) 102 transmits the cycle-defining clock signal.
Upon determining the amount of processing required at any
given time, microprocessor 101 computes an operating
frequency that is sufficient to meet the offered processing load.
Microprocessor 101, which communicates with VCO 102 via
data bus 104, address bus 105 and conductor 106 in the same
manner as with RAM 108 or I/O port 109, writes a digital word
defined by the computed frequency via data bus 104 to VCO
102. VCO 102 gradually adjusts the frequency of the clock
signal transmitted to microprocessor 101 to the computed
frequency in response to the digital word. Reducing the clock
frequency reduces the power consumed by microprocessor 101
and, by reducing the required access rate to the associated
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devices, i.e., ROM 107, RAM 108, and I/O port 109, also
reduces the power consumed by those devices. The power
reduction is substantially directly proportional to the reduction
of the clock frequency.

(col. 2, l. 48-col. 3, l. 6) (Emphasis added).

4. Sheets further teaches the real time frequency computing:
In system 100, the timing of real-time events is controlled by
microprocessor 101 in response to interrupt signals received at
an INT terminal from a fixed-frequency oscillator 103. For
example, microprocessor 101 repeats the process of computing
the required frequency based on the processing load and
writing a digital word to digital VCO 102 at regular intervals
as defined by the interrupt signals from fixed oscillator 103. In
the present embodiment, microprocessor 101 determines its
processing load to control the VCO 102 clock frequency at any
given time by using a linear regression.
(col. 3, ll. 8-21) (Emphases added).
5. Sheets also discloses either a real-time continuous clock
frequency or a discrete clock frequency may be used based on either the
processing backlog, the activity on data bus and address bus (current
processing load) or historical activity records:
Rather than computing the frequency based on the processing
backlog, the activity on data bus 104 and address bus 105
could be monitored and then used as a basis for determining
the required frequency. Instead of using a continuously
variable-frequency clock, selections can be made from a small
number of discrete frequencies. For example, in a battery-
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powered personal computer with an operating system which
includes a sleep state, the microprocessor CPU could be
operated at a low frequency sufficient to keep any dynamic
logic refreshed, e.g., 500 kilohertz, when the operating system
is in the sleep state, and the frequency could then be increased
to a nominal operating frequency, e.g., 10 megahertz, when
wakeup occurs. In some applications, the desired clock
frequency could be determined based on historical activity
records rather than in real time.

(col. 4, l. 58-col. 5, l. 6) (Emphases added).
Fairbanks
6. Fairbanks discloses a method and system for selectively
changing the clock frequencies in accordance with the processing
loads:
In certain tasks performed by a computer system, such as word
processing, it is possible to operate the system clock at a slower
clock rate than is required for computational tasks. . . Thus by
operating at a slower clock frequency and lower voltage the
performance of the system is not degraded from the user's
perspective and the power consumed is reduced. Similarly, if
the system clock is operating at a lower frequency, the devices
utilized in the system may also be operated at a lower voltage
since the reduced voltage will still be adequate to provide
switching at the lower frequency . . . it has been found that
quite adequate performance may be achieved by using a VDD
of approximately 3 volts and a 2.3 mHz system clock frequency
to process information in the word processing mode of
operation. However, when the mode of operation of the
computer involves the computation of numerical data, it is
desirable, under most circumstances, to perform that function
quickly. Accordingly, in the computational mode the power
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supply output is changed from 3 volts to 5 volts and the system
clock frequency changed from 2.3 mHz to 6.6 mHz. Under these
latter conditions the maximum speed of processing is achieved.

(col. 2, ll. 6-36) (Emphases added).

V. ANALYSIS
The Appellant has the opportunity on appeal to the Board of Patent
Appeals and Interferences (BPAI) to demonstrate error in the Examiner’s
position. See In re Kahn, 441 F.3d 977, 985-86 (Fed. Cir. 2006) (citing In re
Rouffet, 149 F.3d 1350, 1355 (Fed. Cir. 1998). The Examiner sets forth a
detailed explanation of a reasoned conclusion of unpatentability in the
Examiner’s Answer. Therefore, we look to Appellant’s Brief to show error
therein. Id.

Nonstatutory Obviousness-type Double Patenting Rejection
ISSUE 1
With respect to claims 22-47, the Appellant contends that the
Examiner has not appropriately compared claim 22-47 of the instant
invention with claims of the cited references as to determining the
differences between the claim language in the instant application and the
claims in the cited patent application and the Thomas reference. Therefore,
Appellant contends that the Examiner improperly rejected claims 22-47
under provisional obviousness-type double patenting (App. Br. 5-13). In
particular, Appellant asserts that Thomas’s temperature reducing technique
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is only applicable to those situations where there is prolonged activity (i.e.,
sustained fast clock frequency and its processor’s temperature has become
too high for proper operation for the processor. (Id. 11).
We disagree with Appellant’s contention. Claims 22, 35, and 44 of
the copending Application 11/123,464 read as follows:
22. A method, comprising the steps of:
determining a work load level associated with a processor; and
using results of said determining for reducing power
consumption associated with said processor as said work load
level decreases.
35. A method, comprising the steps of:
determining and a work load level associated with a processor;
and
using results of said determining for increasing power
consumption associated with said processor as said work load
level increases.
44. A method, comprising the steps of:
determining a work load level associated with a processor; and
using results of said determining for reducing power
consumption associated with said processor as said work load
level decreases and increasing power consumption associated
with said processor as said work load level increases.
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We find that the Examiner compares the claim language of the
appealed claims with the claims of Application No. 11/123,464, and Thomas
reference. The Examiner indicates that the difference between the two sets
of claims is determining the temperature associated with the processor,
which is taught by Thomas (Ans. 9). We agree with the Examiner’s analysis.
We further find Thomas teaches that varying the clock frequency is based on
determining the temperature of the processor (FF 1), and increasing or
decreasing the clock frequency (setting sleep, normal, or fast clocks)
depends on the detected reference temperatures (hot or not hot) of the
processor (FF 2). We thus find that combining the well known element of
determining temperature of a processor and then adjusting the clock
frequency of the processor to prevent overheating and to conserve energy of
the processor as taught by Thomas with the well known technique of
determining the workload level to adjust power supply of the processor as
taught by the copending Application No. 11/123,464 was nothing more than
a “predictable use of prior art elements according to their established
functions.” See KSR, 550 U.S. at 417. As such, we conclude that the
provisional nonstatutory obviousness-type double patenting rejection is
appropriate where the conflicting claims are not identical, but at least some
examined application independent claims are not patentably distinct from the
reference claims because the claims on appeal are either anticipated by, or
would have been obvious over, the reference claims. See e.g., In re Berg,
140 F.3d 1428 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046 (Fed. Cir.
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1993); and In re Longi, 759 F.2d 887 (Fed. Cir. 1985). Accordingly, we
sustain the Examiner’s provisional nonstatutory obviousness-type double
patenting rejection as being unpatentable over claims 22-44 of copending
Application No. 11/123,464 in view of Thomas. (We further note that since
both applications have the same effective priority date of Oct. 30, 1989,
neither is deemed to be an earlier filed application. Accordingly, the
provisional obviousness-type double patenting rejection is ripe for decision.
Compare Ex parte Moncla, No. 2009-006448, 2010 WL 2543659 (BPAI,
June 22, 2010) (precedential), available at
http://www.uspto.gov/ip/boards/bpai/decisions/prec/fd09006448.pdf (noting
that, under the circumstances of that case, it was premature for the Board to
address the Examiner’s provisional obviousness-type double patenting
rejection).

ISSUE 2
With respect to claims 22-47, the Appellant contends that the
Examiner has not appropriately compared claim 22-47 of the instant
invention with claims 24-49 of copending Application 11/137,007. In
particular, claims 24-49 of copending Application 11/137,007 (now US
7,389,438 B2) do not teach the limitations of determining temperature and a
work load level/process demand in claims 22, 35, and 44-47 (App. Br. 14-
24), and is different from the limitations of “detecting temperature” or
“detecting activity associated with a processor”, respectively, of claims of
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copending Application 11/137,007. (Id.)
At the outset we note that copending Application 11/137,007 is now
US 7,389,438 B2. Therefore, the rejection is no longer “provisional,” and is
now a nonstatutory obviousness-type double patenting rejection based upon
the patent. We disagree with the Appellant’s reading of claim language of
which the representative claims 22, 35, 44, (now claims 1, 12, and 23
respectively) read as follows:
1. A method, comprising the steps of:
detecting temperature and activity associated with a processor;
comparing an amount of detected activity with an amount of
detected activity from a previous detecting of activity
associated with said processor and said temperature with a
reference temperature; and
using results of said comparing for reducing power
consumption associated with said processor if said amount of
detected activity is an increase over an amount of detected
activity from a previous determination and said temperature is
at and/or above said reference temperature.
12. A method, comprising the steps of:
detecting temperature and activity associated with a processor;
comparing an amount of detected activity with an amount of
detected activity from a previous detecting of activity
associated with said processor and said temperature with a
reference temperature; and
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using results of said comparing for increasing power
consumption associated with said processor if said amount of
detected activity is an increase over an amount of detected
activity from a previous determination and said temperature is
below said reference temperature.
23. A method, comprising the steps of:
detecting temperature and activity associated with a processor;
comparing an amount of detected activity with an amount of
detected activity from a previous detecting of activity
associated with said processor and said temperature with a
reference temperature; and
using results of said comparing for reducing power
consumption associated with said processor if said amount of
detected activity is an increase over an amount of detected
activity from a previous determination and/or said temperature
is at and/or above a reference temperature and increasing
power consumption associated with said processor if said
amount of detected activity is an increase over an amount of
detected activity from a previous determination and/or said
temperature is below the reference temperature.
Comparing the representative claims of US 7,389,438 B2 with the
claims 22, 35, and 44 of the instant invention, we find that the claim
language “detecting temperature and activity associated with a processor”
and “comparing an amount of the detected activity with . . .” recited in the
representative claims of US 7,389,438 B2 encompasses the claim language
“determining” recited in claims of the instant application. In fact, the steps
of detecting and comparing the representative claims of US 7,389,438 B2
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are not only read as the broader step of determining, which uses different
wording, but also describe how to determine the temperature and activity
(work load level). As such, we conclude that the nonstatutory obviousness-
type double patenting rejection is appropriate where the conflicting claims
are not identical, but at least some examined application independent claims
are not patentably distinct from the reference claims because the examined
application claims are either anticipated by, or would have been obvious
over, the reference claims 1-26 of US 7,389,438 B2 (See e.g., Berg, 140 F.3d
1428; Goodman, 11 F.3d 1046; and Longi, 759 F.2d 887). Accordingly, we
sustain the Examiner’s nonstatutory obviousness-type double patenting
rejection as being unpatentable over claims 1-26 of US 7,389,438 B2.

ISSUE 3
Written Description Requirement
With respect to claims 30, 32, and 41, the Appellant contends that the
Examiner’s rejection under 35 U.S.C. § 112, first paragraph, is improper
because the Specification provides the teachings of power consumption,
clock frequency, and clock speed are increased and decreased by
incremental steps (App. Br. 26).
We agree with the Appellant’s contention. We find that the citation of
the Specification (App.Br. 25-26) as originally filed reasonably conveys to
the artisan that the inventor had possession at that time of the claimed
subject matter, i.e., power consumption, clock frequency, and clock speed
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are increased and decreased by incremental steps (See In re Kaslow, 707
F.2d 1366, 1375 (Fed. Cir. 1983))
Accordingly, we cannot sustain the Examiner’s rejection under 35
U.S.C. § 112, first paragraph.

35 U.S.C. § 103(a) Rejections
ISSUE 4
With respect to claims 24 and 45, the Appellant contends that Sheets
teaches that “the frequency the current job or task to be run is not based on
any analysis of the current program, but is a frequency predetermined for a
previously used program similar to the task or job being run . . . not in
response to the work load level decreasing.” (App. Br. 28). Thus, “[t]he
offered processing load is the backlogged or yet to be processed load” and
“[a]s such, Sheet fails to teach or suggest, ‘reducing power consumption
associated with said processor As said work load level decreases’, as
required by Claim 24.” (Id.). According to the Appellant, “the present
invention is real-time power saving while the work load level decreases.”
(Id. at 29). However, Sheets only teaches the “clock speed is preselected
from the job table and it runs at that same speed until the program has been
completed . . . it does not affect current processing in any manner.” (Id.)
We disagree with the Appellant’s contentions. First, the real time
power saving is not claimed in claims 24 and 35. Moreover, we find Sheets
teaches determining the processing load (work load level) of a processor and
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then adjusting the operating frequency to conserve the power consumption
(FF 3). We also find Sheets further teaches that the timing of computing the
processing load by the processor can be any time (FF 4), which includes the
real time. Furthermore, we find that the processing load can be the activity
on the data bus and the address bus that is current processing load for the
processor (offered processing load) (FF 5). Therefore, Sheets teaches the
claim limitation of adjusting the clock frequency in real time, thus, the
power consumption of the processor decreases as the processing load
changes/decreases, even if we consider the real time power consumption.
Finally, we find Thomas teaches that varying the clock frequency is
based on determining the temperature of the processor (FF 1), and increasing
or decreasing the clock frequency (setting sleep, normal, or fast clocks) in
real time depends on the detected reference temperatures (hot or not hot) of
the processor (FF 2). We, therefore, conclude that combining the well-
known elements – of adjusting the clock frequency of a processor as the
processing load changes – taught by Sheets with the well-known technique –
of determining the operation temperature and the load of a processor to set a
operating clock frequency – taught by Thomas is nothing more than a
“predictable use of prior art elements according to their established
functions.” KSR, 550 U.S., at 417.
Accordingly, we sustain the Examiner’s obviousness rejection of
claims 24 and 45. We further sustain the Examiner’s obviousness
rejection of dependent claims 29, 31, and 33-34, which has not been
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separately argued, and therefore these claims fall with their base claims.
37 C.F.R. § 41.37(c)(1)(vii). See In re Nielson, 816 F.2d 1567, 1572 (Fed.
Cir. 1987).
With respect to claim 25, the Appellant contends that “‘[t]he offered’
processing load is the anticipated load of a program requested to be run —
there is nothing ‘proportional’ about it.” (App. Br. 30).
We disagree with the Appellant’s contention. We find Sheets
expressly teaches that the reduction of the power consumption is directly
proportional to the reduced clock frequency at which the CPU (FF 3), and
the reduced clock frequency is determined by determining the processing
load such as the activity of the data bus and the address bus (FF 5).
Therefore, the decrease of the work load results of decrease of clock
frequency of the CPU that is directly proportional to the reduction of the
power consumption.
Accordingly, we sustain the Examiner’s obviousness rejection of
claim 25.
With respect to claims 26, 30, and 32, the Appellant contends that
Sheets does not teach the reduction in power consumption, clock frequency,
and clock speed is in incremental steps (App. Br. 32-33). We disagree with
the Appellant’s contention. We find Sheets expressly teaches that the power
consumption is directly proportional to the reduced clock frequency (FF 2),
and the reduced clock frequency (or clock speed) can be made from a small
number of discrete frequencies (incremental steps) (FF 5). Therefore, the
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reduction of the power consumption, clock frequency, and clock speed is in
incremental steps.
Accordingly, we sustain the Examiner’s obviousness rejection of
claims 26, 30, and 32.
With respect to claim 27, the Appellant contends that “to the extent
Sheets lowers the frequency of clock signals being sent to microprocessor
101, such lowered frequency is PREDETERMINED and is in response to
reliance on a predetermined job table and NOT-a reduction in power
consumption that continues until no decrease in work load level is detected
over a previous determination of work load level, as required by Claim 27.”
(App. Br. 32).
We disagree with the Appellant’s contention. First, the claim
language does not preclude the situation such that a predetermined
frequency is for a predetermined work load level. Moreover, we find Sheets
teaches that the lowest power consumption corresponding to the lowest
frequency (FF 3) is reached when the CPU/operating system is in sleep state
operated at 500 kilohertz (FF 5). The higher operating frequency of 10
megahertz is corresponding to higher power consumption in wakeup state
(FF 5). We, therefore, conclude that the teachings by Sheets that the
operating clock frequency changes from the wakeup state to sleep state reads
on the claimed language of claim 27.
Accordingly, we sustain the Examiner’s obviousness rejection of
claim 27.
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With respect to claim 28, the Appellant contends that the combination
of Sheets and Thomas does not teach any of the limitations required by the
claim (App. Br. 32-33).
We disagree with the Appellant’s contention. Claim 28 recites “said
reducing power consumption continues until one of: a) no decrease in work
load level is detected over a previous determination of work load level; b)
said processor has reached its minimum power consumption level; and c)
said temperature is at and/or above a reference temperature.” (App. Br.
Claims Appendix 1) (Emphasis added).
First, we note that only one of the three recited limitations needs to be
found in the prior art teachings to meet the claimed invention. Since step A
contains the same language as that of claim 27, as discussed above, we
conclude that Sheets teaches the limitation of claim 28 (FF 5). In addition,
we find Sheets teaches that the minimum power consumption level is the
sleep state of CPU because of the lowest frequency 500 kilohertz (FF 5).
Thus, we conclude that Sheets also teaches step B when the CPU/operating
system reaches the sleep state.
Accordingly, we sustain the Examiner’s obviousness rejection of
claim 28.

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ISSUE 5
With respect to claims 35, 44, and 46-47, the Appellant contends that
Fairbanks fails to teach or suggest the limitations of determining . . . a work
load level associated with a processor or determining processing demand on
the processor (App. Br. 35). According to the Appellant, even if Fairbanks
would have disclosed the argued limitations above, “there is no further
teaching as to how the information is used.”, i.e., using the result of the
determination for increasing/decreasing power consumption associated with
the processor and the temperature is at below/above or at the reference
temperature as the work load level increases/decreases (Id. 35-36).
We disagree with the Appellant’s contentions. First, we note that the
two references (Fairbanks and Thomas) both deal with the control of power
consumption associated an electronic circuit, specifically a microprocessor.
Furthermore, the Fairbanks reference teaches utilizing lower clock frequency
and lower power supply for low processing load such as word processing
while ramping up the higher clock frequency as well as higher power for
higher processing load such as numerical processing (FF 6). Moreover, the
Thomas reference teaches that several discrete clock frequency levels are
determined and used so that when no activity detected sleep frequency is
used, when there is activity and the chip temperature is not hot, i.e., below
the reference temperature, the fast clock is used, and when there is activity
and the chip temperature is hot, i.e., at or above the reference temperature,
the normal clock (slower than fast clock) is used (FF 2). Thus, we conclude
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that the combination of Fairbanks and Thomas teaches or fairly suggests all
the limitations in claims 44 and 47. The knowledge of ramping up/down the
clock frequency depends on the activity and the reference temperature of the
processor detected would have been within the skill in the art, as evidenced
by Thomas. The Thomas reference also provides the ample evidence of a
motivation to combine the references by teaching conserving power and
preventing overheat of the processor (FF 2). We find the scope of claims 35
and 46 is much broader than that of claims 44 and 47. As discussed above,
we also conclude that the combination of Fairbanks and Thomas teaches or
fairly suggests all the limitations in claims 35 and 46.
Accordingly, we sustain the Examiner’s obviousness rejection of
claims 35, 44, and 46-47. We further sustain the Examiner’s obviousness
rejection of dependent claims 42-43, which have not been separately
argued, and therefore these claims fall with their base claims. 37 C.F.R. §
41.37 (c)(1)(vii). See In re Nielson, 816 F.2d 1567, 1572 (Fed. Cir. 1987).

ISSUE 6
With respect to claim 36, the Appellant contends that neither Sheets
nor Fairbanks teaches or fairly suggests that “an amount of said increasing
power consumption is proportional to the increase of said work load level”,
required by claim 36 (App. Br. 38-39).
We disagree with the Appellant’s contention. We find Sheets teaches
that the power consumption is directly proportional to the operating clock
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frequency (FF 3), and the clock frequency of a CPU is increasing from 500
kilohertz to 10 megahertz when the work load level from the sleep state
changes to the wakeup state (FF 5). We also find Fairbanks teaches that
when the work load level increases from word processing to numerical data
computation, the power consumption increases from 3 volts to 5 volts, which
teaches proportionally changing of power consumptions (FF 6).
Accordingly, we sustain the Examiner’s obviousness rejection of
claims 36.
With respect to claims 38-39, the Appellant contends that the
Examiner has not identified any teaching within the cited references for the
teachings in claims 38-39 (App. Br. 39).
Claim 39 recites “said increasing power consumption continues until
one of: a) no increase in work load level is detected over a previous
determination of work load level; b) said processor has reached its maximum
power consumption level; and c) said temperature is at and/or above a
reference temperature.” The body of claim 38 is the same as the step A of
claim 39.
First, we note that there is only one of the three limitations needed to
be found in the prior art teachings, as discussed above. Furthermore, we
find Sheets teaches that the lowest power consumption corresponding the
lowest frequency (FF 3) is reached when the CPU/operating system is in
sleep state operated at 500 kilohertz, and the consumption level increases
until CPU is in wakeup state, the operating frequency is 10 megahertz (FF
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5). In our view that Sheets’ teaching the process that the operating clock
frequency changes from the sleep state (lower power consumption level) to
the wakeup state (higher power consumption level) reads on the claimed
language of claim 39, which increase of the power consumption continues
while the clock frequency is raised from 500 kilohertz until no increase in
work load level is detected over a predetermined work load level (the
wakeup state is detected/reached).
Since step A of claim 39 contains the same language as that of claim
38, as discussed above, we conclude that Sheets teaches the limitation of
claims 38-39. In addition, we find Fairbanks teaches that the maximum
power consumption level (5 volts) is reached the numerical data
computation mode that the clock speed is maximum speed (FF 6). Thus, we
additionally conclude that Fairbanks teaches step B of claim 39.
Accordingly, we sustain the Examiner’s obviousness rejection of
claims 38-39. Further, we sustain the Examiner’s obviousness rejection of
dependent claims 37, 40, and 41, which have not been separately argued,
and therefore fall with their base claims. 37 C.F.R. § 41.37(c)(1)(vii). See
Nielson, 816 F.2d at 1572.

VI. CONCLUSION
Based on our consideration of the totality of the record before us,
having weighed the evidence of obviousness found in the teachings of the
applied references with the Appellant’s countervailing evidence and
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arguments for nonobviousness, we conclude that the claimed invention
encompassed by appealed claims 24-47 would have been unpatentable as a
matter of law under 35 U.S.C. § 103(a).
We also conclude that the Examiner has not erred in provisionally
rejecting claims 24-47 under nonstatutory obviousness-type double
patenting over claims 24-44 of copending Application No. 11/123,464
in view of Thomas. We also conclude that the Examiner has not erred
in rejecting claims 24-47 under nonstatutory obviousness-type double
patenting over claims 1-26 of US 7,389,438 B2.
However, we conclude that the Examiner has erred in finding that
claims 30, 32, and 41 fail to comply with the written description requirement
under 35 U.S.C. § 112, first paragraph.

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VII. ORDER
We affirm the obviousness rejections of claims 24-47 under 35 U.S.C.
§ 103(a).
We also affirm the provisional nonstatutory obviousness-type double
patenting rejections of claims 24-47.
We reverse the written description requirement rejection of claims 30,
32, and 41 under 35 U.S.C. § 112, first paragraph.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED

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P.O. BOX 644474, M/S3999
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