Ex Parte Wang et al

Patent Trial and Appeal Board

Mar 26, 2013

11679820 (P.T.A.B. Mar. 26, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte CHI-LIE WANG and BERTAN TEZCAN
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Appeal 2010-010157
Application 11/679,820
Technology Center 3900

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Before DEBRA K. STEPHENS, HUNG H. BUI, and MIRIAM L. QUINN,
Administrative Patent Judges.

STEPHENS, Administrative Patent Judge.

DECISION ON APPEAL
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Application 11/679,820

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Appellants appeal under 35 U.S.C. § 134(a) (2002) from a final
rejection of claims 1, 3-6, 8-16, 18-22, 26, and 27. We have jurisdiction
under 35 U.S.C. § 6(b). Claims 2, 7, 17, and 23-25 have been canceled.
We AFFIRM-IN-PART.
Introduction
According to Appellants, the invention relates to a system and method
for configuring DMA engines to implement DMA transfers from a serial
buffer to a system memory on a serial interface (Spec. 2, [0006]).

STATEMENT OF THE CASE

Exemplary Claims
Claims 1 and 15 are exemplary claims and are reproduced below:

1 . A serial buffer comprising:

a plurality of queues configured to store data packets received from a
host;

a direct memory access (DMA) engine coupled to receive data packets
read from the queues;

a plurality of DMA register sets, wherein each of the DMA register
sets is configured to store parameters that define a corresponding
DMA channel of the DMA engine, and wherein each of the DMA
register sets include a start address register configured to store a start
address and a stop address register configured to store a stop address,
wherein the start address and the stop address define a unique buffer
within a system memory, and wherein each of the DMA register sets
include a wrap/stop register configured to store a wrap stop identifier
that indicates whether or not the buffer is accessed in a wraparound
manner; and
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circuitry for selecting one of the DMA register sets to configure the
DMA engine, thereby enabling the DMA engine to transfer the
received data packets to the system memory using the corresponding
DMA channel.

15. A method of performing a DMA transfer in a serial buffer,
comprising:

retrieving a first data packet from a first queue of the serial buffer;
then,

selecting a first DMA register set in response to information included
in a header of the first data packet retrieved from the first queue of the
serial buffer; and then,

configuring a DMA engine to transfer the first data packet in response
to the first DMA register set;

retrieving a second data packet from a second queue of the serial
buffer;

selecting a second DMA register set corresponding with the second
queue of the serial buffer; and

configuring the DMA engine to transfer the second data packet in
response to the second DMA register set.

References
McRoberts US 5,530,902 Jun. 25, 1996
Mears US 2003/0061431 A1 Mar. 27, 2003

Rejections
(1) Claims 1, 3-6, 9-11, 14, 15, 18-22, 26, and 27 stand rejected
under 35 U.S.C. § 102(b) as being anticipated by McRoberts.
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(2) Claims 8, 12, 13, 16, and 20 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over McRoberts and Mears.

ISSUE 1
35 U.S.C. § 102(b): claims 1, 3-6, 9-11, 14, 26, and 27
Appellants argue their invention is not anticipated by McRoberts
because McRoberts fails to describe “a direct memory access (DMA) engine
coupled to receive data packets read from the queues” (App. Br. 14, 15).
Specifically, Appellants contend McRoberts does not disclose the data
packets read from the packet memory 20, which the Examiner points to as
being the claimed “queues,” are received by the DMA controller 64 (App.
Br. 14-15; Reply Br. 4). Therefore, Appellants assert, McRoberts fails to
disclose a DMA engine coupled to receive data packets read from the queue
(App. Br. 15; Reply Br. 4-5).

Issue 1: Has the Examiner erred in finding McRoberts discloses “a
direct memory access (DMA) engine coupled to receive data packets read
from the queues,” as recited in claim 1?

ANALYSIS
We agree with Appellants. The Examiner finds Packet Memory 20
includes the recited “queues” (Ans. 3 and 16-17). Additionally, the
Examiner finds DMA 64 in Figure 2 of McRoberts discloses the DMA
engine. However, we are not convinced McRoberts describes that the DMA
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engine is coupled to receive data packets read from the queues. Indeed,
Figure 2 does not illustrate a pathway from the Memory 20 to the DMA
controller. Nor does the Abstract state that the data packets are transmitted
from the memory to an input buffer through the DMA controller. Therefore,
McRoberts does not disclose “a direct memory access (DMA) engine
coupled to receive data packets read from the queues,” as recited in
independent claim 1 and as commensurately recited in independent claims
26 and 27.
Since we agree with at least one of the arguments advanced by
Appellants, we need not reach the merits of Appellants’ other arguments.
Accordingly, the Examiner erred in finding McRoberts discloses the
invention as recited in independent claims 1 and claims 3-6, 9-11, 14, 26,
and 27, not separately argued. Therefore, the Examiner erred in rejecting
claims 1, 3-6, 9-11, 14, 26, and 27 under 35 U.S.C. § 102(b) for anticipation
by McRoberts.

ISSUE 2
35 U.S.C. § 103(a): claims 8, 12, 13, 16, and 20
Appellants assert their invention is not obvious over McRoberts and
Mears based on the arguments set forth with respect to claim 1 (App. Br. 21-
22).
For the reasons set forth above in Issue 1, we find the Examiner has
erred in finding McRoberts describes “a direct memory access (DMA)
engine coupled to receive data packets read from the queues,” as recited in
claim 8. Claims 12 and 13 depend from independent claim 1, and thus,
stand with that claim. Accordingly, the Examiner erred in finding the
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combination of McRoberts and Mears teaches or suggests the invention as
recited in claims 8, 12, and 13. Therefore, the Examiner erred in rejecting
claims 8, 12, and 13 under 35 U.S.C. § 103(a) for obviousness over
McRoberts and Mears.

ISSUE 3
35 U.S.C. § 102(b): claims 15 and 18-22
Appellants argue their invention is not anticipated by McRoberts
because McRoberts fails to describe “selecting a second DMA register set
corresponding with the second queue of the serial buffer,” as recited in
independent claim 15 (App. Br. 19, 20). Specifically, Appellants argue
McRoberts teaches the buffer manager is selected in response to contents of
the incoming data packet and not that the buffer manager used to control the
incoming data packet is selected to correspond with a queue that has
provided the data packet (App. Br. 19)(citing col. 2, ll. 54-56). Further,
Appellants contend McRoberts fails to teach two different manners of
“selecting a first DMA register set” and “selecting a second DMA register
set” (Reply Br. 8).
Issue 3: Has the Examiner erred in finding McRoberts discloses
“selecting a second DMA register set corresponding with the second queue
of the serial buffer,” as recited in claim 15?

ANALYSIS
We are not persuaded the Examiner erred in finding McRoberts
describes this limitation. Appellants’ arguments are not commensurate with
the scope of the claims. Specifically, claim 15 recites “selecting a second
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DMA register set corresponding with the second queue” (emphasis added).
Since McRoberts discloses the DMA register set (buffer manager) is
activated based on the translated buffer type number of the packet data in the
second queue (Fig. 3, element 78), we find McRoberts describes selecting
the DMA register set associated with the second queue. Additionally, the
claim does not recite different manners of selecting.
Accordingly, we are not persuaded the Examiner erred in finding
McRoberts describes “selecting a second DMA register set corresponding
with the second queue of the serial buffer,” as recited in independent claim
15 and as recited in dependent claims 18-22, not separately argued.
Therefore, the Examiner did not err in rejecting claims 15 and 18-22 under
35 U.S.C. §102(b) for anticipation by McRoberts.

ISSUE 4
35 U.S.C. § 103(a): claims 16 and 20
Appellants assert their invention is not obvious over McRoberts and
Mears based on the arguments set forth with respect to claim 15 (App. Br.
21-22).
For the reasons set forth above in Issue 3, we find the Examiner has
not erred in finding McRoberts describes the invention as recited in claim
15. Claims 16 and 20 depend from independent claim 15, and thus, fall with
claim 15. Accordingly, the Examiner did not err in finding the combination
of McRoberts and Mears teaches or suggests the invention as recited in
claims 16 and 20. Therefore, the Examiner did not err in rejecting claims 16
and 20 under 35 U.S.C. § 103(a) for obviousness over McRoberts and
Mears.
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DECISION
The Examiner’s rejection of claims 1, 3-6, 9-11, 14, 26, and 27 under
35 U.S.C. § 102(b) as being anticipated by McRoberts is reversed.
The Examiner’s rejection of claims 8, 12, and 13 under 35 U.S.C.
§ 103(a) as being unpatentable over McRoberts and Mears is reversed.
The Examiner’s rejection of claims 15 and 18-22 under 35 U.S.C.
§ 102(b) as being anticipated by McRoberts is affirmed.
The Examiner’s rejection of claims 16 and 20 under 35 U.S.C.
§ 103(a) as being unpatentable over McRoberts and Mears is affirmed.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2011).

AFFIRMED-IN-PART

ELD