Ex Parte Vorbach et al

Patent Trial and Appeal Board

Oct 24, 2017

14223793 (P.T.A.B. Oct. 24, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/223,793 03/24/2014 Martin VORBACH PACT-020-DE-PCT-US-2C1 1970
73481 7590 10/26/2017
Alliacense Limited LLC
2310 Homestead Rd
#C 1-505
Los Altos, CA 94024-7339
EXAMINER
BROPHY, MATTHEW J
ART UNIT PAPER NUMBER
2191
NOTIFICATION DATE DELIVERY MODE
10/26/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
emi @ alliacense.com
ip @ alliacense. com
ned @ alliacense. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MARTIN VORBACH, FRANK MAY, MARKUS WEINHARDT,
and JO AO MANUEL PAIVA CARDOSO1
Appeal 2017-002761
Application 14/223,793
Technology Center 2100
Before CAROLYN D. THOMAS, AMBER L. HAGY, and
MICHAEL M. BARRY, Administrative Patent Judges.
THOMAS, Administrative Patent Judge.
DECISION ON APPEAL
Appellants seek our review under 35 U.S.C. § 134(a) of the
Examiner’s Final Rejection of claims 13—29, all the pending claims in the
present application. Claims 1—12 are canceled. See Claims Appendix. We
have jurisdiction over the appeal under 35 U.S.C. § 6(b).
We AFFIRM.
1 The Appellants name PACT XPP Technologies AG as the real party in
interest. App. Br. 1.
Appeal 2017-002761
Application 14/223,793
The present invention relates generally to a conventional processor
unit and an array processor having a multidimensional arrangement of
arithmetic units. See Abstract.
Claim 13 is illustrative:
13.
DSP);
units;
A method for operating a system on a chip having:
a conventional processor (CISC, RISC, VLIW,
an array processor having an array of arithmetic
a shared memory between the conventional
processor and the array processor;
the array having an operation information address
generator for addressing the shared memory; the method
comprising:
the conventional processor providing an address of
array operation information in said shared memory to said
operation information address generator; and
the array processor autonomously loading
operation information during runtime into the array processor
from the shared memory addressed by said operation
information address generator.
Appellants appeal the following rejections:
Rl. Claims 13, 14, and 26—29 are rejected under 35 U.S.C. § 103(a)
as being unpatentable over Greenbaum (US 6,077,315, June 20, 2000),
Appleby-Allis (US 2003/0033514 Al, Feb. 13, 2003), and Coleman (US
6,895,452 Bl, May 17, 2005);
R2. Claims 15—22 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Greenbaum, Appleby-Allis, Coleman, and Barroso (US
2002/0010840 Al, Jan. 24, 2002); and
R3. Claims 23—25 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Greenbaum, Appleby-Allis, Coleman, and Shyr (US
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Application 14/223,793
6,871,341 B1, Mar. 22,2005).
We review the appealed rejections for error based upon the issues
identified by Appellants, and in light of the arguments and evidence
produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential).
ANALYSIS
Issue: Did the Examiner err in finding that the cited art collectively
teaches or suggests autonomously loading operation information from the
shared memory, as set forth in claim 13?
Appellants contend that “Coleman discloses an execution unit that is
provided operands from memory 800 to execution unit 130 via address
generator 750. Operands are the data a processor processes. They are not
instructions” (App. Br. 7). Appellants further contend that “Opcodes, which
corresponds to configuration or operational information are provided by
opcode generator 720. The opcodes themselves do not come from memory
800” {id. at 8). Appellants also contend that Appleby-Allis “does not
disclose any FPGA that loads new configurations or operation information
into ITSELF during runtime” {id. at 9).
In summary, Appellants contend that “none of the reference [s] come[]
anywhere close to disclosing an array processor that receives from a
conventional processor the address in shared memory of operation
information and that autonomously loads such operation information into the
array processor during runtime” (App. Br. 10).
First, we note, as a matter of claim construction, that neither claim 13
nor Appellants’ Specification defines “operation information.” Instead,
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Application 14/223,793
Appellants’ Specification merely notes that “the VPU provides its own
mechanism for loading and controlling configurations ... in which the
configurations of the VPU are loaded into a memory .... [T]he CPU may
refer the VPU to the memory locations .... The VPU may then load the
configurations” (4:6—13). As such, we agree with the Examiner that
Appellants’ “claim does not require ‘instructions’ or ‘opcodes’ but more
broadly . . . [encompasses] data used in an operation” (see Ans. 17), for
example, configuration data to be loaded. In any case, Appellants concede
that “Greenbaum[’s] ‘configurations’ comprise the claimed ‘operation
information’” (Reply Br. 2).
The Examiner finds that “Coleman teaches or suggests an ‘address
generator’ that generates addresses” {id.), and Appellants’ argument
“a) ignores the teachings of Greenbaum that unquestionably teach
reconfiguration instructions stored in a shared memory and b) ignores that
applicant’s claim does not require ‘instructions’ or ‘opcodes’ but more
broadly ‘operation information’ which plainly includes data used in an
operation” (id. ). Stated differently, the Examiner finds that “a) Greenbaum
teaches a method of reconfiguring a reconfigurable array using
reconfiguration instructions stored in a shared memory and b) Coleman
teaches an address generator for loading information from a shared memory”
(id. at 18; see also Final Act. 3). We agree with the Examiner.
Specifically, Greenbaum discloses “[f]our memory buses 216 run
vertically through the rows for moving information into and out of the array
108. .. . For loading configurations 116 and for saving and restoring array
108 state, the entire width of memory buses 216 is used” (5:23—32).
Coleman discloses “an execution unit is tightly coupled to a shared,
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Application 14/223,793
configurable memory system. Sequence control signals drive a DMA
controller and address generator to control the transfer of data from the
shared memory” (Abstract). In other words, Greenbaum discloses a
reconfigurable array using loaded configurations from the shared memory
and Coleman discloses an address generator controlling the transfer of data
from the shared memory. Thus, we agree with the Examiner that the
combined teachings of Greenbaum and Coleman teach or suggest loading
operation information from the shared memory.
Appellants’ argument against Coleman separately from Greenbaum
does not persuasively rebut the combination made by the Examiner. One
cannot show non-obviousness by attacking references individually, where
the rejections are based on combinations of references. In re Merck & Co.,
Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986); In re Keller, 642 F.2d 413, 425-
26 (CCPA1981).
Regarding the claimed “autonomously loading operation
information,” the Examiner finds that “a broad but reasonable construction
of [Appellants’] claimed ‘array processor’ includes multiple [Field
Programmable Gate Arrays (FPGAs)], as in Appleby-Allis which load
reconfiguration instructions and reconfigure each other [FPGA] at runtime”
(Ans. 18). In other words, the Examiner interprets the claimed “array
processor” to include two or more FPGA’s able to reconfigure each other.
In reply, Appellants contend that “Appleby-Allis used two different arrays
precisely because the prior art disclosed no means for an array processor to
load its own configurations” (Reply Br. 5). We disagree with Appellants.
We highlight that Appleby-Allis discloses “[t]he present invention
relates to reconfigurable hardware and more particularly to a self-
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Application 14/223,793
configuring logic device” (12) (emphasis added). Therefore, contrary to
Appellants’ assertion, Appleby-Allis does appear to view its device
including an array processor (i.e., having a first and second FPGA) as
performing a self-configuring procedure, i.e., autonomously loading
configuration information (see 19). Thus, we find unavailing Appellants’
contention that Appleby-Allis’ use of two different arrays cannot equate to
an autonomously loading of operation information given that Appleby-Allis
expressly states that it is self-configuring.
Accordingly, we sustain the Examiner’s rejection of claim 13.
Appellants do not argue separate patentability for the dependent claims. See
App. Br. 4—10. We, therefore, also sustain the Examiner’s rejections of
claims 14—29.
DECISION
We affirm the Examiner’s § 103(a) rejections Rl—R3.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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