Ex Parte Trantham

Patent Trial and Appeal Board

Jul 20, 2016

12351283 (P.T.A.B. Jul. 20, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/351,283 0110912009 Jon David Trantham
12675 7590 07/22/2016
Cesari & Reed, LLP -
Seagate Technology LLC
1114 Lost Creek Boulevard
Suite 430
Austin, TX 78746
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1100-STLl 4858 8525
EXAMINER
CHAUDRY,MUJTABAM
ART UNIT PAPER NUMBER
2112
NOTIFICATION DATE DELIVERY MODE
07/22/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
usptomail@cesari-reed.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JON DAVID TRANTHAM
Appeal2015-000530
Application 12/351,283
Technology Center 2100
Before JEAN R. HOMERE, HUNG H. BUI, and KEVIN C. TROCK,
Administrative Patent Judges.
BUI, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 seeks our review under 35 U.S.C. § 134(a) of the
Examiner's Final Office Action rejecting claims 1---6, 8-12, and 21-28,
which are all claims pending on appeal. App. Br. 1. We have jurisdiction
under 35 U.S.C. § 6(b).
We AFFIRM.2
1 According to Appellant, the real party in interest is Seagate Technology
LLC. App. Br. 1.
2 Our Decision refers to Appellant's Appeal Brief filed July 24, 2014 ("App.
Br."); Reply Brief filed October 8, 2014 ("Reply Br."); Examiner's Answer
mailed August 8, 2014 ("Ans."); Final Office Action mailed December 18,
2013 ("Final Act."); and original Specification filed January 9, 2009
("Spec.").
Appeal2015-000530
Application 12/351,283
STATEMENT OF THE CASE
Conventional data memory devices (e.g., flash drives or memory
sticks) support interfaces through which commands and/ or data are sent
from a controller. However, the commands, data, parameters, and/or status
information, for example, associated with various operations can contain
errors. As such, Appellant's invention proposes adding an error detection
component in a data memory device to detect errors occurring on data
received at an interface prior to the data being stored to a memory array.
Spec. 1:20-27, Abstract.
Claim 1 is independent and describes Appellant's invention, as
reproduced below with disputed limitations in italics:
1. A device comprising:
a semiconductor memory package including:
a memory array within the semiconductor memory
package;
an interface configured to connect to an external data
storage controller and to receive data and send data;
a chip select input configured to allow the data storage
controller to select the semiconductor memory package for an
operation; and
an error detection component within the semiconductor
memory package configured to detect errors occurring on data
received from the external data storage controller at the
interface, detection of the errors occurring prior to the data
being stored to the memory array.
App. Br. 20 (Claims App'x.) (emphasis added).
Examiner's Rejection
Claims 1---6, 8-12, and 21-28 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Terasaki (US Patent 6,388,919 B2; May 14,
2
Appeal2015-000530
Application 12/351,283
2002) and Kaizu (US Publication 2008/0258758 Al; Oct. 23, 2008). Ans.
2-11.
ANALYSIS
In support of the rejection of claim 1 and similarly claim 21, the
Examiner finds Terasaki teaches:
a semiconductor package including (i.e., Figure 2, reference
number 1 and col. 5, lines 12-19); a memory array within the
semiconductor package (i.e., Figure 2, reference numbers 2-0, 2-
1, 2-2, 2-3); an interface configured to connect to an external data
storage controller and to receive data and send data (i.e., Figure
2, interface 7, controller 3 and memory array 2-0--2-3 and col. 5,
lines 38-44; The Examiner would like to point out that the
controller 3 is integrated in a single semiconductor chip.); a chip
select input configured to allow the data storage controller to
select the semiconductor package for an operation (i.e., Figure 2,
reference number 10 and col. 6, lines 14-40).
ii .. ns. 2 (citing Terasaki 5:12-20, 38--44, 6:14--40, Fig. 2).
Terasaki's Figure 2 is reproduced below:
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