Ex Parte Tanioka

Patent Trial and Appeal Board

Mar 15, 2013

11038133 (P.T.A.B. Mar. 15, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte TAKAHIRO TANIOKA
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Appeal 2010-008013
Application 11/038,133
Technology Center 2100
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Before KRISTEN L. DROESCH, JUSTIN BUSCH, and
LYNNE E. PETTIGREW, Administrative Patent Judges.

PETTIGREW, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-9. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

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STATEMENT OF THE CASE
Introduction
According to Appellant, the invention relates to a computer apparatus
with a memory controller having a link monitoring circuit that detects a
communication cutoff between the memory controller and an I/O controller.
Spec. 11; Abstract.
Claims 1, 2, 6, and 7 are independent. Claim 1 is illustrative of the
invention (disputed limitation italicized):
1. A computer apparatus comprising:
a plurality of cells each having a processor, a main
memory device, and a memory controller for connecting said
processor and said main memory device to each other, within
each cell of a plurality of cells said memory controller is
interposed between said processor and said main memory
device;
a plurality of I/O buses associated respectively with said
cells for connection to a plurality of peripheral devices; and
a plurality of I/O controllers for connecting the memory
controllers of said cells and said I/O buses to each other, each
I/O controller corresponding to a single said memory controller,
each I/O controller separate from said memory controller;
said memory controller comprising:
a link monitoring circuit for detecting a communication
cutoff between the memory controller and the I/O controller
corresponding thereto;
an error reply generating circuit for receiving a message
indicative of a detected communication cutoff from said link
monitoring circuit, and generating an error reply for a
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transaction being processed which is issued from said processor
to one of said peripheral devices;
a selector for outputting a reply sent from one of the
peripheral devices through the I/O controller corresponding
thereto while the computer apparatus is in normal operation,
and outputting the error reply generated by said error reply
generating circuit when the communication cutoff is detected;
and
a control circuit for sending the reply or the error reply
received from said selector to the corresponding processor as a
source for issuing said transaction.
Rejections on Appeal
The Examiner rejected claims 1, 4, 6, and 9 under 35 U.S.C. § 102(b)
as being anticipated by Shaw (US 6,618,825 B1, Sept. 9, 2003). Ans. 3-6.
The Examiner rejected claims 2, 3, 5, 7, and 8 under 35 U.S.C.
§ 103(a) as being unpatentable over Shaw and Goldman (US 5,423,025,
June 6, 1995). Ans. 6-8.
Issues on Appeal
Based on Appellant’s arguments, the issues on appeal are:
(1) Does Shaw teach “a memory controller comprising . . . a link
monitoring circuit for detecting a communication cutoff between the
memory controller and the I/O controller,” as recited in claim 1 and similarly
recited in claim 6 (App. Br. 15-18)?
(2) Do the combined references teach or suggest “a memory controller
comprising . . . a diagnostic I/F circuit for receiving fault information of said
I/O controllers which is collected by said service processor,” as recited in
claim 2 and similarly recited in claim 7 (App. Br. 19-20)?
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ANALYSIS
We have reviewed the Examiner’s rejection in light of Appellant’s
contentions that the Examiner has erred. We agree with Appellant’s
conclusions. We highlight and address specific findings and arguments for
emphasis as follows.
Rejection of Claims 1 and 6 under 35 U.S.C. § 102(e)
In finding that Shaw teaches “a memory controller comprising . . . a
link monitoring circuit for detecting a communication cutoff between the
memory controller and the I/O controller,” as recited in claims 1 and 6, the
Examiner relies on Shaw’s disclosure of a coordinated hierarchy of timers in
a computing device in which a timer monitoring a transaction may report a
time-out condition to a higher level timer. Ans. 4, 9-10 (citing Shaw, col. 6,
ll. 43-65; col. 12, ll. 51-65). The Examiner finds Shaw discloses that errors
are detected within the I/O system (I/O system chip 300 shown in Figure 3)
and reported to a hierarchically higher level, e.g., the memory controller
(CPU interface controller 309 in Figure 3). Ans. 10. The Examiner further
finds that “CPU fetch timer 203 within the memory controller also detects
errors . . . by the error report transmitted from the I/O system.” Ans. 10; see
also Ans. 4, 9 (citing Shaw, col. 10, ll. 33-37 (“[T]he ‘log error information’
step . . . logs error information at timer 203 which indicates that the error
occurred at timer lower in the hierarchy than timer 203.”)). In addition, the
Examiner cites column 14, lines 37-38 of Shaw, which provides in Table I a
time-out value for an “I/O Subsystem fetch response time” as one of many
transactions suitable for timing. Ans. 4. Based on these teachings, the
Examiner finds that “Shaw teaches a link detecting circuit in the memory
controller for detecting a communication cutoff between the memory
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controller and the I/O controller corresponding thereto [no CPU requested
data available from the I/O subsystem 300 due to the malfunction or error in
the I/O subsystem 300].” Ans. 10.
Appellant contends that the Examiner has erred in combining CPU
fetch timer 203 of Shaw with the I/O Subsystem fetch response time shown
in Table I to disclose a link monitoring circuit in the memory controller as
recited in claims 1 and 6. App. Br. 15. First, Appellant argues that nothing
in Table I states that the I/O Subsystem fetch response time is used by CPU
fetch timer 203. Id. Appellant also argues that none of the discussion of
CPU fetch timer 203 in Shaw discusses the failure of the I/O controller to
respond. App. Br. 16. Appellant further argues that even if CPU fetch timer
203 exemplifies reporting an error response to higher level devices, the
Examiner does not provide anticipatory support in Shaw for the recited
limitation. App. Br. 17.
Appellant has persuaded us that the Examiner erred. We agree that
the Examiner has not pointed to anything in Shaw that teaches a link
monitoring circuit for detecting a communication cutoff between the
memory controller and the I/O controller. Shaw does not disclose that CPU
fetch timer 203 detects the failure of the I/O controller to respond, and the
Examiner has not found that any other component of Shaw’s CPU interface
controller (i.e., memory controller) detects a cutoff of communication with
the I/O controller. Shaw’s reference to an I/O Subsystem fetch response
time is not sufficient under § 102(e) to establish that Shaw discloses a link
monitoring circuit for detecting a communication cutoff between the
memory controller and the I/O controller.
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For at least these reasons, we do not sustain the Examiner’s rejection
of claims 1 and 6 under 35 U.S.C. § 102(e) as anticipated by Shaw, nor do
we sustain the Examiner’s § 102(e) rejection of dependent claims 4 and 9.
Rejection of Claims 2 and 7 under 35 U.S.C. § 103(a)
Instead of the link monitoring circuit in claims 1 and 6, claims 2 and 7
recite “a service processor . . . for collecting fault information detected by
LSI circuits and units,” and “a memory controller comprising . . . a
diagnostic I/F circuit for receiving fault information of said I/O controllers
[controller in claim 7] which is collected by said service processor.” The
Examiner cites timer 304A in Shaw as corresponding to the recited
diagnostic I/F circuit for receiving fault information. Ans. 7 (citing Shaw,
col. 12, ll. 59-65, which states “timer 304A preferably times out and
transmits an error condition to . . . CPU interface controller 309”). As
Appellant correctly asserts, timer 304A is a PCI timer in the I/O system chip,
not in the memory controller (i.e., CPU interface controller), and monitors
whether requested data is returned from a PCI controller chip within a
defined time period. App. Br. 19; Shaw, col. 12, ll. 59-61; col. 13, ll. 6-13.
Although the Examiner finds generally that “a logic of the I/O controller
relates to a logic of the memory controller” (Ans. 11), the Examiner has not
explained how PCI timer 304A in Shaw teaches or suggests an I/F circuit in
the memory controller for receiving fault information from a service
processor. Furthermore, the Examiner has not asserted that Goldman
teaches the recited limitation.
For at least these reasons, we do not sustain the Examiner’s rejection
of claims 2 and 7 under 35 U.S.C. § 103(a) over Shaw and Goldman, nor do
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we sustain the Examiner’s § 103(a) rejection of dependent claims 3, 5, and
8.
CONCLUSION
On the record before us, we conclude that the Examiner erred in
rejecting claims 1, 4, 6, and 9 under 35 U.S.C. § 102(e) as being anticipated
by Shaw, and claims 2, 3, 5, 7, and 8 under 35 U.S.C. § 103(a) as being
unpatentable over Shaw and Goldman.
DECISION
The Examiner’s rejection of claims 1-9 is reversed.

REVERSED

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