Ex Parte Symes et al

Patent Trial and Appeal Board

Jun 30, 2016

12588412 (P.T.A.B. Jun. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/588,412 10/14/2009
73459 7590 07/05/2016
NIXON & V ANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11 TH FLOOR
ARLINGTON, VA 22203
FIRST NAMED INVENTOR
Dominic Hugo Symes
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
JRL-550-1205 3309
EXAMINER
PARTRIDGE, WILLIAM B
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
07/05/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
PTOMAIL@nixonvan.com
pair_nixon@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DOMINIC HUGO SYMES
and
SIMON ANDREW FORD
Appeal2014-004962
Application 12/588,412
Technology Center 2100
Before CARLA M. KRIVAK, MICHAEL J. STRAUSS, and
MICHAEL A. BARRY, Administrative Patent Judges.
KRIVAK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-15. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Appeal2014-004962
Application 12/588,412
STATEMENT OF THE CASE
Appellants' invention is directed to a "data processing apparatus and
method for performing rearrangement operations" (Spec. 1 :4--5).
Independent claim 1, reproduced below, is exemplary of the subject
matter on appeal.
1. A data processing apparatus comprising:
a register data store having a plurality of registers, each register for
storing a plurality of data elements;
processing circuitry responsive to control signals to perform
processing operations on said data elements;
an instruction decoder responsive to program instructions to generate
said control signals;
said instruction decoder being responsive to a group of at least one but
no more than N program instructions, where N is an odd plural number, to
generate control signals to control said processing circuitry to perform a
rearrangement process comprising:
obtaining as source data elements the data elements stored in N
registers of said register data store as identified by the at least one
program instruction of the group;
performing a rearrangement operation to rearrange the source
data elements between an N-way interleaved order and a
de-interleaved order in order to produce a sequence of result data
elements; and
outputting the sequence of result data elements for storing in
the register data store.
REFERENCES and REJECTIONS
The Examiner rejected claims 1-15 under 35 U.S.C. § 103(a) based
upon the teachings of Sidwell (US 6,145,077; publ. Nov. 7, 2000) and
Deodhar (US 4,567,594; publ. Jan. 28, 1986).
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Appeal2014-004962
Application 12/588,412
ANALYSIS
The Examiner finds Sidwell discloses all the features of Appellants'
claimed invention except for the limitation "N is an odd plural number"
(Final. Act. 4). The Examiner then finds Deodhar discloses 3-way
interleaving (Final Act. 4--5). Thus, the Examiner states, it would be
obvious to modify Sidwell's "N equals 2" to include 3-way interleaving as
taught by Deodhar to obtain Appellants' invention (Final Act. 5). We do not
agree.
Appellants contend Deodhar merely mentions 3-way interleaving, but
not how it is performed (App. Br. 12). That is, although the Examiner finds
Deodhar discloses three registers to accommodate three way interleaving,
the registers merely accumulate check byte data so each register contains
one of the required check bytes (App. Br. 13). As "each section has three
registers and produces one check bytes [sic] for each code word, the
collective 24 registers already store the 24 check bytes in the required three-
way interleaved order for adding to the interleaved user bytes" (App. Br. 13-
14). Thus, there is no interleaving (or de-interleaving) operation disclosed in
Deodhar; rather Deodhar merely describes registers that accommodate
generated check bytes in an interleaved form (App. Br. 14). Because the
input is already interleaved and the output is already interleaved, no
rearrangement is performed between an interleaved order and de-interleaved
order (App. Br. 14). We agree.
As to the combination of Sidwell and Deodhar, the Examiner merely
states Deodhar discloses 3-way interleaving, and because Sidwell discloses
2-way interleaving it would be obvious for Sidwell to employ 3-way
interleaving (Final Act. 4--5, "the combination would allow Sidwell to
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Appeal2014-004962
Application 12/588,412
incorporate changes to allow for where N is odd plural, 3 in this example").
We do not agree. As Appellants assert, however, and we agree, Sidwell may
disclose it is possible "to use 'a group of at least one but no more than N
program instructions' when N is an even number;" when N is an odd plural
number, as claimed, this is not true. Instead, Sidwell discloses using one
instruction to operate on the contents of two registers (Reply Br. 2).
We therefore do not sustain the Examiner's rejection of claims 1-15
over the combination of Sidwell and Deodhar, as neither of the references,
alone or in combination, teaches or suggests an "instruction decoder being
responsive to a group of at least one but no more than N program
instructions, where N is an odd plural number, to generate control signals to
control said processing circuitry to perform a rearrangement process."
DECISION
The Examiner's decision rejecting claims 1-15 is reversed.
REVERSED
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