Ex Parte Suh

Board of Patent Appeals and Interferences

Sep 8, 2010

10880110 (B.P.A.I. Sep. 8, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte WOON-SIK SUH
____________________

Appeal 2009-007042
Application 10/880,1101
Technology Center 2100
____________________

Before LANCE LEONARD BARRY, HOWARD B. BLANKENSHIP, and
JAY P. LUCAS, Administrative Patent Judges.

LUCAS, Administrative Patent Judge.

DECISION ON APPEAL2

1 Application filed June 29, 2004. Appellants claim the benefit under
35 U.S.C. § 119 of various applications dating to September 20, 2003. The
real party in interest is Samsung Electronics Co., LTD.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

Appeal 2009-007042
Application 10/880,110

STATEMENT OF THE CASE
Appellant appeals from a final rejection of claims 14 to 33 under
authority of 35 U.S.C. § 134(a). The Board of Patent Appeals and
Interferences (BPAI) has jurisdiction under 35 U.S.C. § 6(b). Claims 1 to 13
are cancelled.

We affirm-in-part.

Appellant’s invention relates to eliminating redundant resources in a
communication device. (See Spec. 4, ll. 3 to 11.) In the words of Appellant:
[T]he shared local memory [stores] data associated
with both the AP [i.e., application processor] and
the modem, and … [is] used as a shared interface
memory between the AP and the modem. In such
configuration, interface control data, as well as AP
associated data such as CPU data are stored in the
memory. With … the use of a common platform
for communication … the communication device
including the AP, the modem, and the shared
memory can be integrated.
(Spec. 11, l. 16 to 12, l. 2).
The following illustrate the claims on appeal:
Claims 14 and 33:
14. A method of accessing a shared memory in a
communication device having a signal
modulator/demodulator (modem) for effecting
radio communications and an application
processor (AP) having a central processing unit,
comprising:

clocking the AP, the modem, and the shared
memory by a common clock;
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Application 10/880,110

accessing the shared memory by both the
AP and the modem at different edges of a clock
cycle by accessing CPU data to and from the
shared memory by the AP using a rising edge or a
falling edge of a clock cycle and accessing modem
data to and from the shared memory by the modem
using the other edge of the clock cycle not used by
the AP.

33. A method of accessing a shared memory in a
communication device having a signal
modulator/demodulator (modem) for effecting
radio communications and an application
processor (AP) having a central processing unit,
comprising:

clocking the AP, the modem, and the shared
memory by a clock;

accessing the shared memory by both the
AP and the modem at different edges of a clock
cycle.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Jones US 6,480,429 B2 Nov. 12, 2002
(filed Feb. 12, 2001)
Patel US 2004/0024955 A1 Feb. 05, 2004
(filed Apr. 01, 2003)

REJECTION
The Examiner rejects the claims as follows:

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Application 10/880,110

Claims 14 to 33 stand rejected under 35 U.S.C. § 103(a) for being
obvious over Patel in view of Jones.

We have only considered those arguments that Appellant actually
raised in the Briefs. Arguments that Appellant could have made but chose
not to make in the Briefs have not been considered and are deemed to be
waived. See 37 C.F.R. § 41.37(c)(1)(vii).

ISSUES
The issues involve whether Appellant has shown that the Examiner
erred in rejecting the claims under 35 U.S.C. § 103(a). The first issue
specifically turns on whether the Examiner’s combination of the Jones and
Patel references disclose Appellant’s claim limitation “accessing the shared
memory by both the AP and the modem at different edges of a clock cycle
by accessing CPU data to and from the shared memory by the AP using a
rising edge or a falling edge of a clock cycle and accessing modem data to
and from the shared memory by the modem using the other edge of the clock
cycle not used by the AP,” as recited in independent claim 14. The second
issue specifically turns on whether Jones and Patel’s disclosures meet the
claim limitation “accessing the shared memory by both the AP and the
modem at different edges of a clock cycle” of independent claim 33.

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Application 10/880,110

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
Disclosure
1. Appellant has invented a method of accessing a shared memory by
both an application processor (AP) and a modem at different edges of the
same clock cycle. (See claim 14.) As claimed, the application processor
accesses CPU data in the shared memory on a rising edge of a clock cycle,
and the modem accesses modem data in the shared memory using the other
edge of the clock cycle not used by the application processor (id.).
Patel
2. The Patel reference discloses that either an application processor or a
baseband processor access a memory (¶¶ [0011], [0036], and [0037]). In
“pass-through mode,” in which the application processor is inactive, the
baseband processor accesses memory.
Jones
3. The Jones reference discloses a double-density memory (e.g., DDR)
that sends data to a processor on both the rising and falling edges of the
same clock cycle (col. 2, ll. 5 to 8; col. 3, l. 65 to col. 4, l. 1). Jones further
discloses that data may be sent on either the rising edge or the falling edge of
the clock cycle (col. 2, ll. 17 to 18).

PRINCIPLE OF LAW
Appellant has the burden on appeal to the Board to demonstrate
Examiner error. See In re Kahn, 441 F.3d 977, 985-86 (Fed. Cir. 2006).
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Appeal 2009-007042
Application 10/880,110

ANALYSIS
Arguments with respect to the rejection
of claims 14 to 33
under 35 U.S.C. § 103(a)

The Examiner has rejected the noted claims for being obvious over
Patel and Jones, pages 3 to 13. Regarding claim 14, the Examiner relies on
Patel’s disclosure of an application processor (cited as Appellant’s claimed
“AP”) and a baseband processor (cited as the “modem,” as claimed)
accessing a memory controller (cited as Appellant’s “shared memory”). The
Examiner combines Patel with Jones’s disclosure of accessing data stored in
a DDR (double-density memory) device on both the rising and falling edge
of a clock cycle.3 In reply, Appellant contends that the combination of Patel
and Jones fails to disclose the claimed “accessing” step. We find persuasive
Appellant’s argument for claim 14.
In Patel, either the application processor or the baseband processor
(but not both processors) are active (i.e., accessing the memory) during a
single clock cycle. (See FF#2.) The Jones reference discloses a double-
density memory (e.g., DDR) that sends data on both the rising and falling
edge of the same single clock cycle (FF#3). However, only one of Jones’s
devices (i.e., the processor) accesses the double-density memory (id.).
We find the combination of Patel and Jones fails to disclose or suggest
Appellant’s claimed “accessing” step, such that the “application processor”
accesses memory on “a rising edge” and the claimed “modem” accesses
memory on “the other edge of the clock cycle not used by the AP” of the

3 We note that the background of Jones’s disclosure indicates that data may
be accessed on either the rising or falling edge of a clock cycle (FF#3).
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Application 10/880,110

claimed “clock cycle” (i.e., the same “clock cycle”). Accordingly, we
reverse the rejection of claims 14 to 32.
Regarding claim 33, Appellant argues that because Patel involves
switching between “passthrough mode” and “regular mode” to access shared
memory, “it would not be possible to effect this change of modes in a timely
manner such that the application processor could access the shared memory
at one edge of a clock cycle in a normal mode and then the mode could be
switched to a passthough [sic] mode in time for the baseband processor to
access the shared memory through the application processor at the other
edge of a clock cycle in the passthough [sic] mode.” (App. Br. 18, top to
middle).
We find unconvincing Appellant’s above-stated argument because the
argument is not commensurate with the scope of claim 33. The “accessing”
step of claim 33 merely requires “accessing … at different edges of a clock
cycle.” Patel discloses sending data from two types of processors, an
application processor and a broadband processor. (See FF#2.) In addition,
Jones does indeed disclose that data may be sent on either a rising edge or a
falling edge of a clock cycle (FF#3). Thus the broad claim language is met.
In view of Patel and Jones’s above-stated disclosures and since
Appellant’s argument is outside the scope of the claim language, we find
that Appellant has not shown error in the Examiner’s rejection of claim 33.
CONCLUSIONS OF LAW
Based on the findings of facts and analysis above, we conclude that
Appellant has shown error in the Examiner’s rejection of claims 14 to 32.
No error was demonstrated in the rejection of claim 33.

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Appeal 2009-007042
Application 10/880,110

DECISION
We reverse the Examiner’s rejection of claims 14 to 32. We affirm
the rejection of claim 33.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

peb

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