Ex Parte Sudhakar et al

Patent Trial and Appeal Board

Oct 30, 2018

13789467 (P.T.A.B. Oct. 30, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/789,467 03/07/2013
20230 7590 11/01/2018
V orys, Sater, Seymour and Pease LLP
1909 K St., NW
9th Floor
WASHINGTON, DC 20006-1152
FIRST NAMED INVENTOR
Ranganathan Sudhakar
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
075803.000051 2725
EXAMINER
MEHTA, JYOTI
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
11/01/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patlaw@vorys.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RANGANATHAN SUDHAKAR and PARTHIV POTA
Appeal2018-003852
Application 13/789,467
Technology Center 2100
Before ELENI MANTIS MERCADER, NORMAN H. BEAMER, and
ADAM J. PYONIN, Administrative Patent Judges.
MANTIS MERCADER, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's
final rejection of claims 1, 3-6, 8-15, 17, and 18, which constitute all the
pending claims in this application. We have jurisdiction under 35 U.S.C.
§ 6(b ).
We affirm.
1 Appellants identify Imagination Technologies, LLC as the real party in
interest (App. Br. 1).
Appeal2018-003852
Application 13/789,467
THE INVENTION
Appellants' claimed invention is directed to a processor "configured
to identify a branch instruction immediately followed by an architectural
delay slot" in which a "single bonded instruction comprising the branch
instruction immediately followed by the architectural delay slot is created"
(Abstract).
Independent claim 1, reproduced below, is representative of the
subject matter on appeal:
1. A processor in electronic hardware, comprising:
an instruction buffer; and
an instruction fetch unit connected to the instruction
buffer, the instruction fetch unit configured to
identify a branch instruction immediately followed
by an architectural delay slot;
create a single bonded instruction comprising the
branch instruction immediately followed by the architectural
delay slot; and
load the single bonded instruction into the
instruction buffer.
App. Br. 10 (Claims Appendix).
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is the following:
Adir et al. US 2012/0054560 Al Mar. 1, 2012
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Application 13/789,467
Kenneth C. Yeager, The MIPS RI 0000 Superscalar Microprocessor Vol. 16
Issue 2 MICRO. (April, 1996).
Slane et al., Delayed Branches with Packed Instruction Stream AN IP.COM
PRIOR ART DATABASE TECHNICAL DISCLOSURE (Apr. 5, 2005).
Anonymous, Don't We All Need ARMs? An Introduction to the ARM System
Architecture, INTERNET ARCHIVE WAYBACK MACHINE (Nov. 10, 2016),
https://web.archive.org/web/20090712101340/http://cs.umd.edu/class/fall20
01/cmsc411/proj0 I/arm/home.html.
John Hennessy and David Patterson, Computer Architecture: A Quantitative
Approach" (5th Ed.) (Sept. 8, 2015)
http://store.elsevier.com/product.jsp?isbn=9780123838728.
REJECTIONS
The Examiner made the following rejections:
Claims 1, 3, 4, 8, and 9 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Slane and Hennessy. Final Act. 3.
Claim 5 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Slane, Hennessy, and "RISC machine." Final Act. 6.
Claim 6 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Slane, Hennessy, and Yeager. Final Act. 7.
Claims 10-13, 17, and 18 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Slane, Hennessy, and Adir. Final Act. 8.
Claim 14 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Slane, Hennessy, Adir, and "RISC machine." Final Act.
12.
Claim 15 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Slane, Hennessy, Adir, and Yeager. Final Act. 13.
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Application 13/789,467
ISSUE
The pivotal issue is whether the Examiner erred in finding the
combination of Slane and Hennessy teaches or suggests the limitations
recited in independent claim 1, and similarly recited in independent claim
10.
ANALYSIS
We adopt the Examiner's findings in the Answer and we add the
following primarily for emphasis. We note that if Appellants failed to
present arguments on a particular rejection, we will not unilaterally review
those uncontested aspects of the rejection. See Ex parte Frye, 94 USPQ2d
1072, 1075 (BPAI 2010) (precedential); Hyatt v. Dudas, 551 F.3d 1307,
1313-14 (Fed. Cir. 2008) (The Board may treat arguments Appellants failed
to make for a given ground of rejection as waived).
Appellants argue that "no possible combination of the teachings of
Slane with Hennessy ... would have or could have resulted in the claimed
subject matter" (Reply Br. 5). Particularly, Appellants contend Hennessy's
macro-op fusion "involves fused instructions where the branch is the second
instruction in the fused entity, whereas according to the present invention the
branch instruction is the first instruction in the fused entity" (Reply Br. 2,
emphasis in original, citing App. Br. 5). Appellants further point to Slane's
JMP Gump) and P JMP (packed jump) instructions as being "part of Slane' s
provided instruction set" (Reply Br. 3), and thus "there manifestly would be
no need, no point and no purpose for attempting to 'fuse' them with any
other instruction fetched by an instruction fetch unit" (Reply Br. 4).
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Application 13/789,467
We are not persuaded by Appellants' arguments. The Examiner finds,
and we agree, that
Slane teaches a processor with a branch instruction and a delay
slot (Page 1 1st paragraph). Hennessy teaches fusing two
instructions in the fetch unit. Slane also teaches bonding a
jump and a delay slot in particular (3rd and 4th paragraphs).
Starting with the processor of Slane that has a branch
instruction and a delay slot, one of ordinary skill would modify
the processor of Slane to fuse two instructions. As Slane also
teaches bonding a jump and a delay slot in particular, the
combination would result in the processor of Slane bonding the
jump and the delay slot in particular
(Ans. 5). Appellants argue the references individually, and in contradiction
to the Examiner's findings, arrive at a combination that requires (1)
Hennessy' s particular ordering of bonding the branch instruction as the
second instruction in the fused entity, and (2) Slane's instruction set
containing the JMP and P JMP instructions. The test for obviousness is not
whether the claimed invention is expressly suggested in any one or all of the
references, but whether the claimed subject matter would have been obvious
to those of ordinary skill in the art in light of the combined teachings of
those references. See In re Keller, 642 F.2d 413,425 (CCPA 1981).
Appellants do not address and challenge the Examiner's findings regarding
the combined teachings of Hennessy and Slane.
Appellants additionally argue that "the only motivation for the attempt
to somehow combine Hennessy with Slane is to reject claim 1 of the present
application through a hindsight attempt at reconstruction" (Reply Br. 4). We
are not persuaded, because the skilled artisan is "a person of ordinary
creativity, not an automaton," and this is a case in which the skilled artisan
would "be able to fit the teachings of multiple patents together like pieces of
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Application 13/789,467
a puzzle." KSR International Co. v. Teleflex Inc., 550 U.S. 398,421
(2007)). KSR at 421.
Accordingly, we sustain the Examiner's rejection of independent
claim 1 and independent claim 10 commensurate in scope, and dependent
claims 3---6, 8, 9, 11-15, 17, and 18 not separately argued. See App. Br. 4--9.
CONCLUSION
The Examiner did not err in finding the combination of Slane and
Hennessy teaches or suggests the limitations recited in independent claim 1,
and similarly recited in independent claim 10.
DECISION
The Examiner's decision rejecting claims 1, 3-6, 8-15, 17, and 18
under 35 U.S.C. § 103(a) is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(l )(iv).
AFFIRMED
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