Ex Parte Su et al

Board of Patent Appeals and Interferences

Jan 20, 2012

11160694 (B.P.A.I. Jan. 20, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte YAO-CHUN SU and JUI-MING WEI
____________

Appeal 2009-012691
Application 11/160,694
Technology Center 2100
____________

Before MAHSHID D. SAADAT, ROBERT E. NAPPI, and
JEFFREY S. SMITH, Administrative Patent Judges.

SMITH, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2009-012691
Application 11/160,694

2
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-5, 8-12, 15-18, and 21, which are all the claims
remaining in the application. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

Invention
Appellants’ invention relates to a computer system having a central
processing unit, a north bridge electrically connected to the central
processing unit, memory electrically connected to the north bridge, a south
bridge electrically connected to the north bridge, and a peripheral device
electrically connected to the south bridge. The south bridge includes a
register for storing a plurality of pre-fetched read data to provide the pre-
fetched read data to the peripheral device. The north bridge has an address
queue module for storing an address of the pre-fetched read data, and a
snooping module for checking whether a data value corresponding to the
address is updated by the CPU. The north bridge assists the south bridge in
obtaining and maintaining the pre-fetched read data for high efficiency and
accuracy of read caching of the south bridge. Abstract.

Representative Claim
1. A chip set electrically connected to a central processing
unit (CPU) and a peripheral device, comprising:

a south bridge electrically connected to the peripheral
device, the south bridge having a register for storing a plurality
of pre-fetched data to provide the pre-fetched data to the
peripheral device while being requested, wherein an adjoining
Appeal 2009-012691
Application 11/160,694

3
data of a peripheral data is fetched as the pre-fetched data, and
the peripheral data is requested by the peripheral device, and
the addresses of the pre-fetched data and the addresses of the
peripheral data are sequential; and

a north bridge electrically connected to the CPU and the
south bridge, the north bridge comprising:

an address queue module for storing addresses of
the pre-fetched data; and

a snooping module for snooping a cache in the
CPU according to the addresses of the pre-fetched data in
the address queue to determine whether the pre-fetched
data is updated and to ensure data coherence between the
register and the cache.

Prior Art
Jones US 6,470,429 B1 Oct. 22, 2002

Examiner’s Rejections
Claims 1-5, 8-12, 15-18, and 21 stand rejected under 35 U.S.C.
§ 102(b) as being anticipated by Jones.

ISSUE
Did the Examiner err in finding that Jones describes “an address
queue module for storing addresses of the pre-fetched data,” where the pre-
fetched data is stored in the register of the south bridge?

Appeal 2009-012691
Application 11/160,694

4
ANALYSIS
Appellants contend that Jones does not disclose “an address queue
module for storing addresses of the pre-fetched data,” where the pre-fetched
data is stored in the register of the south bridge. App. Br. 6. The Examiner
finds that the north bridge of Jones includes a cache coherency controller
that maintains the coherence of data stored in each of the processor caches in
the computer system. According to the Examiner, the cache coherency
controller corresponds to the claimed address queue module. Ans. 4, 13.
However, Jones does not disclose that the cache coherency controller,
which maintains coherence of data stored in each processor cache shown in
Figure 1, maintains coherence of data stored in the local cache 262 or local
cache 272 of the south bridge shown in Figure 2. In fact, Jones discloses
that the data that is pre-fetched and stored in the cache of the south bridge
are generally tagged as non-cachable. The non-cachable data can be
retrieved and stored in the local cache of the south bridge while bypassing
the cache coherence directory lookups and bus snoops. Col. 7, ll. 16-29.
We do not agree with the Examiner (Ans. 13) that the cache
coherency controller disclosed by Jones describes the “address queue
module” recited in claim 1. We do not sustain the rejection of claim 1 and
corresponding dependent claims 2-5 under 35 U.S.C. § 102. Independent
claim 8 has a limitation similar to that of claim 1 for which the rejection
fails. We do not sustain the rejection of claim 8 and corresponding
dependent claims 9-12 and 15 under 35 U.S.C. § 102.
Claim 16 recites “storing addresses of the pre-fetched data in a north
bridge,” where the pre-fetched data is stored in a south bridge. The
Examiner has not established that Jones describes storing addresses of the
Appeal 2009-012691
Application 11/160,694

5
pre-fetched data in a north bridge as discussed in our analysis of claim 1.
We do not sustain the rejection of claim 16 and corresponding dependent
claims 17, 18, and 21 under 35 U.S.C. § 103.

CONCLUSION
The Examiner erred in finding that Jones describes “an address queue
module for storing addresses of the pre-fetched data,” where the pre-fetched
data is stored in the register of the south bridge.

DECISION
The rejection of claims 1-5, 8-12, 15-18, and 21 under 35 U.S.C.
§ 102(b) as being anticipated by Jones is reversed.

REVERSED

msc