Ex Parte Strumpen et al

Patent Trial and Appeal Board

Jun 30, 2016

13917126 (P.T.A.B. Jun. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/917,126 06/13/2013 Volker Strumpen
61043 7590 06/30/2016
IBM CORPORATION (MH)
c/o MITCH HARRIS, ATTORNEY AT LAW, L.L.C.
P.O. BOX 7998
A THENS, GA 30604
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
AUS920080471 US3 8132
EXAMINER
THAMMAVONG, PRASITH
ART UNIT PAPER NUMBER
2137
MAILDATE DELIVERY MODE
06/30/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte VOLKER STRUMPEN and MATTEO FRIGO
Appeal2015-002744
Application 13/917,126
Technology Center 2100
Before ROBERT E. NAPPI, CARLA M. KRIVAK, and
JEFFREY A. STEPHENS, Administrative Patent Judges.
KRIVAK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Appeal2015-002744
Application 13/917, 126
STATEMENT OF THE CASE
Appellants' invention is directed to a tiled storage array with move-to-
front reorganization that "move[s] a requested value to a front-most storage
element of [the] array" (Title; Abstract).
Independent claim 1, reproduced below, is exemplary of the subject
matter on appeal.
1. A storage circuit, including:
multiple storage tiles corresponding to a single level of
storage access that provides for arbitrary access to any one of
the multiple storage tiles, wherein values stored within the
storage circuit are associated with unique corresponding ones of
the multiple storage tiles, and wherein a particular one of the
multiple storage tiles is a front-most tile having an interface
connection at which responses to read access requests directed
at any of the multiple storage tiles are provided to a requesting
device from a storage within the front-most tile; and
control logic for accessing the values within the multiple
storage tiles, wherein the control logic moves the values among
the multiple storage tiles according to a placement heuristic in
response to an access to one of the multiple storage tiles while
maintaining the uniqueness of the values within the multiple
storage tiles to move a requested value to the front-most tile,
and wherein the control logic further moves the values among
the multiple storage tiles according to a global clock, whereby
multiple move-to-front operations are simultaneously
maintained in-progress among the multiple storage tiles.
REFERENCES and REJECTIONS
The Examiner rejected claims 1-20 under non-statutory obviousness-
type double patenting over claims 1-20 of Strumpen (US 8,527,726 B2; Sep.
3, 2013).
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Application 13/917, 126
The Examiner rejected claims 1-20 under 35 U.S.C. § 103(a) based
upon the teachings of Qiu (US 2003/0236961 Al; Dec. 25, 2003) and
Forster (US 6,839,809B1; Jan. 4, 2005).
ANALYSIS
Non-Statutory Obviousness-Type Double Patenting Rejection
Appellants do not address the Examiner's rejection of claims 1-20
based upon obviousness-type double patenting over Strumpen. We therefore
proforma sustain the double patenting rejection of claims 1-20.
Rejection under 35 US.C. § 103(a)
The issue before us is whether Appellants have shown error in the
Examiner's findings with respect to 35 U.S.C. § 103.
With respect to independent claim 1, the Examiner finds Qiu teaches
Appellants' claimed storage circuit in which "multiple move-to-front
operations are simultaneously maintained in-progress among the multiple
storage tiles" (Final Act. 7 (citing Qiu i-fi-145, 53)).
Appellants contend the Examiner erred. Particularly, Appellants
assert there is no disclosure in Qiu of maintaining multiple move-to-front
operations simultaneously in-progress among multiple tiles as claimed (App.
Br. 11; Reply Br. 7). We agree with Appellants the Examiner has not shown
multiple move-to-front operations simultaneously in-progress among
multiple storage tiles in Qiu. Paragraph 45 of Qiu describes dynamic
reassignment of a memory unit within and between queues and layers, but
does not disclose the dynamic reassignment performs multiple move-to-front
operations simultaneously among Qiu's memory blocks or nodes. Paragraph
53 of Qiu describes an operation by which an external storage memory block
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Appeal2015-002744
Application 13/917, 126
is added to memory block/node 301 a from which another memory block
moves downwards to the next node 301 b, but does not disclose multiple
simultaneous move-to-front operations towards node 301a. Paragraph 119
of Qiu cited by Examiner in connection with the claimed "moves the values
among the multiple storage tiles according to a global clock global" (Ans. 8;
Final Act. 7 (citing Qiu i-f 119)) also does not teach multiple simultaneous
move-to-front operations (App. Br. 11; Reply Br. 7, 8).
The Examiner has not shown how Forster makes up for the above-
noted deficiency in Qiu. Forster discloses moving a data object to the head
of a first queue; however, the cited portions of Forster do not disclose
multiple simultaneous move-to-front operations towards the head of the first
queue (see Forster Fig. 3).
Absent findings that Qiu or Forster teaches multiple move-to-front
operations simultaneously maintained in-progress among multiple storage
tiles as required by each of the independent claims 1, 10, and 19, on the
record before us, we do not sustain the Examiner's rejection under 35 U.S.C.
§ 103(a) of claims 1, 10, and 19, and claims 2-9, 11-18, and 20 dependent
therefrom. We do not address Appellants' remaining arguments regarding
the § 103 rejection because this issue is dispositive with respect to all claims.
DECISION
The Examiner's decision rejecting claims 1-20 under non-statutory
double patenting is affirmed.
The Examiner's decision rejecting claims 1-20 under
35 U.S.C. § 103(a) is reversed.
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Appeal2015-002744
Application 13/917, 126
Because we have affirmed at least one ground of rejection with
respect to each claim on appeal, we affirm the Examiner's decision rejecting
claims 1-20. See 37 C.F.R. § 41.50(a)(l).
AFFIRMED
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