Ex Parte Sproule et al

Patent Trial and Appeal Board

Sep 6, 2017

14152601 (P.T.A.B. Sep. 6, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/152,601 01/10/2014 Patrick Alan SPROULE NVDA/SC-13-0405-US1 1930
102324 7590 09/08/2017
Arte.ois T aw Omim T T P/NVTDTA
EXAMINER
7710 Cherry Park Drive Suite T #104
Houston, TX 77095
AISAKA, BRYCE M
ART UNIT PAPER NUMBER
2851
NOTIFICATION DATE DELIVERY MODE
09/08/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
kcruz @ artegislaw.com
ALGdocketing @ artegislaw.com
rsmith @ artegislaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PATRICK ALAN SPROULE,
SHRIVATHSA BHARGAVRAVICHANDRAN,
KARTHIK SUNDARAM, and KEVIN SAVIDGE
(Applicant NVIDIA CORPORATION)1
Appeal 2016-006034
Application 14/152,601
Technology Center 2800
Before GEORGE C. BEST, CHRISTOPHER L. OGDEN, and
JENNIFER R. GUPTA, Administrative Patent Judges.
GUPTA, Administrative Patent Judge.
DECISION ON APPEAL2
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s final
decision rejecting claims 1—20. We have jurisdiction under 35 U.S.C.
§ 6(b). We affirm.
1 Applicant (hereinafter “Appellant”) identifies the real party in interest as
NVIDIA Corporation. Appeal Br. 3.
2 In this Decision, we refer to the Specification filed January 10, 2014
(“Spec.”), the Final Office Action mailed March 24, 2015 (“Final Act.”), the
Appeal Brief filed November 16, 2015 (“Appeal Br.”), the Examiner’s
Answer mailed March 22, 2016 (“Ans.”), and the Reply Brief filed May 23,
2016 (“Reply Br.”).
Appeal 2016-006034
Application 14/152,601
The subject matter on appeal relates to integrated circuit (IC) chip
design, and more specifically to floorplan annealing using perturbation of
automated macro placement results. Spec. 11. Claim 1, reproduced below
from the Claims Appendix of the Appeal Brief, is illustrative of the claims
on appeal.
1. A method of designing a floorplan for an integrated
circuit, the method comprising:
executing one or more automated placement processes via
a processor on one or more seed floorplans to generate at least
one output floorplan for each of the one or more seed floorplans
by performing an iterative process that continues until a
predetermined resolution criterion is met, wherein the one or
more automated placement processes are included in a plurality
of preselected automated placement processes;
computing a quality score for each output floorplan; and
based on the quality scores, selecting one of the at least
one output floorplans for further execution via at least one
automated placement process included in the plurality of
preselected automated placement processes.
Appeal Br. 16 (Claims Appendix).
REJECTIONS
The Examiner maintains the following rejections on appeal:
Rejection 1: Claims 1—20 stand rejected under 35 U.S.C. § 101 as
directed to non-statutory subject matter;
Rejection 2: Claims 1—16, 18, and 20 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over Gupta et al. (US 2007/0168898 Al, published
July 19, 2007) (“Gupta”) in view of Takahashi et al. (US 6,792,583 Bl,
issued September 14, 2004) (“Takahashi”);
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Rejection 3: Claim 17 stands rejected under 35 U.S.C. § 103(a) as
unpatentable over Gupta in view of Takahashi, and further in view of Sinha
et al. (US 2010/0031217 Al, published February 4, 2010) (“Sinha”); and
Rejection 4: Claim 19 stands rejected under 35 U.S.C. § 103(a) as
unpatentable over Gupta in view of Takahashi, and further in view of Kahng
(US 7,873,929 B2, issued January 18, 2011) (“Kahng”).
DISCUSSION
Rejection 1 — Patent-eligible subject matter
We focus our discussion on independent claim 1 directed to a method
of designing a floorplan for an integrated circuit, claim 6 directed to a non-
transitory computer readable medium, and claim 20 directed to a computing
device.
We have reviewed the ground of rejection set forth by the Examiner,
Appellant’s arguments, and the Examiner’s response. On this record, we are
unpersuaded that the Examiner erred reversibly in determining that the
claims do not comply with 35 U.S.C. § 101 for the reasons set forth by the
Examiner in the Final Office Action and the Examiner’s Answer. We add
the following.
Section 101 defines the scope of patent-eligible subject matter as “any
new and useful process, machine, manufacture, or composition of matter, or
any new and useful improvement thereof.” 35 U.S.C. § 101. The Supreme
Court, however, has long interpreted § 101 to include an exception: “[ljaws
of nature, natural phenomena, and abstract ideas” are not patentable. See,
e.g., Alice Corp. Pty. Ltd. v. CLS Bank Inti, 134 S. Ct. 2347, 2354 (2014)
(internal quotation and citation omitted). To determine whether an invention
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claims ineligible subject matter requires the application of the two-step test
described in Mayo Collaborative Servs. v. Prometheus Labs., Inc., 566 U.S.
66, 78—79 (2012) and further explained in Alice Corp. Pty. Ltd. v. CLS Bank
Int’l, 134 S. Ct. 2347, 2354 (2014). The first step requires a determination
as to whether the claims at issue are directed to a patent-ineligible concept,
such as an abstract idea. See Alice, 134 S. Ct. at 2355.3 The second step
requires examination of “the elements of the claim to determine whether it
contains an ‘inventive concept’ sufficient to ‘transform’ the claimed abstract
idea into a patent-eligible application.” Id. at 2357 (quoting Mayo 566 U.S.
at 72, 79). Claims directed to, or reciting, systems are also ineligible under
§ 101 if the hardware recited by the claims add nothing significantly more
than the underlying abstract idea. Id. at 2360.
The Examiner has adequately explained why the recitations of the
claims as a whole are directed to abstract ideas that our reviewing court has
previously deemed patent-ineligible. Ans. 3^4 (citing Content Extraction &
Transmission v. Wells Fargo Bank, N.A., 776 F.3d 1343, 1347-48 (Fed.
Cir. 2014) (rejecting as ineligible claims directed to (1) collecting data,
2) recognizing certain data within the collected data set, and 3) storing that
recognized data in a memory)). The Examiner determines the claims are
3 The Supreme Court has suggested that claims “purporting] to improve the
functioning of the computer itself,” or “improve[ing] an existing
technological process” might not succumb to the abstract idea exception.
Alice, 134 S. Ct. 2358—59; see also Enfish, LLC v. Microsoft Corp. 822 F.3d
1327, 1335—36 (Fed. Cir. 2016) (inquiring in the first step of the Alice
inquiry “whether the focus of the claims is on the specific asserted
improvement in computer capabilities ... or, instead, on a process that
qualifies as an ‘abstract idea’ for which computers are invoked merely as a
tool.”).
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directed to non-statutory subject matter because the executing, computing,
and selecting elements in the claims are similar to manipulating (e.g.,
recognizing and reorganizing) data using mathematical correlations which is
“considered as an abstract idea under the Alice test.” Ans. 3. Specifically,
the Examiner finds that the “executing” step recited in claim 1 is similar to
collecting and recognizing data based on a criterion, the “computing” step is
similar to manipulating existing information to generate additional
information, and the “selecting” step is similar to reorganizing and
recognizing certain data within the collected data set. See Ans. 3. The
Examiner finds that manipulation of mathematical relationships/formulas in
a process of designing a floorplan for an integrated circuit is an abstract idea
“because the algorithms themselves are not. . . improvement to another
technology or technical field, [and] the algorithms are also not. . .
improvements to the functioning of the computer itself because the software
[has] already been developed and run in a computer system.” Id. (citing
Spec. 14). In addition, the Examiner finds that claim 1 and its dependent
claims do not have any additional limitations that would qualify as
“significantly more” than the abstraction idea itself. See Ans. 4. The
Examiner, therefore, determines that the claims are patent ineligible under
35 U.S.C § 101.
Appellant contends that a problem that arises directly out of
automated integrated circuit design is the occurrence of false-positives that
result from current automated schemes. Reply Br. 4. Appellant argues that
the claims cannot properly be interpreted as an “abstract idea” under the first
prong of the two-step Alice test because the claims focus on a specific
improvement in the capabilities of a computer—“reducing [the likelihood of
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such false-positives] typically encountered with conventional automated
[integrated circuit] design processes, which increases execution speeds and
improves convergence rates on optimal solutions [] rather than merely
adding a computer as a component to a well-understood process.” Reply
Br. 5. Appellant further argues that the claimed approach provides a
technical solution to a technical problem arising out of automated integrated
circuit design technology, thereby improving the functioning of the
computer itself. Reply Br. 5; see also id. at 4 (indicating the solution
includes computing a quality score for each output floorplan, and based on
the quality scores, selecting one of the at least one output floorplans for
further execution via at least one automated placement process). Appellant
also contends that the pending claims are not directed to the abstract idea
because “the step of computing quality scores necessarily involves
generating new data; therefore, the claimed approach is necessarily
functionally different than merely organizing data.” Id. at 5 (emphasis
omitted).
Additionally, Appellant argues that the claims are subject matter
eligible under the second prong of the two-step Alice test because the claims
include additional elements, e.g., computing a quality score of each output
floorplan from an automated placement process, then selecting at least one
output floorplan for further execution via at least one automated placement
process based on the computed quality scores, and those steps amount to
“significantly more” than an abstract idea itself. Id. at 6—7. Further,
Appellant argues that “[bjecause the claims are directed towards a very
specific way of designing IC floorplans, ... the claims cannot be properly
interpreted as preempting all uses of an abstract idea.” Id. at 6.
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Appellant’s arguments do not persuade us that the claims are not
properly rejected under § 101. Claim 1 is directed to a method of designing
a floorplan for an integrated circuit that executes one or more automated
placement processes via a processor on one or more seed floorplans to
generate at least one output floorplan, computes a quality score for each
output floorplan, and based on the quality scores, selects one of the at least
one output floorplans for further execution via at least one automated
placement process. See Spec. 132 (disclosing that the executing, computing
and selecting steps recited in claim 1 are performed by software
tools/software modules). Claim 6 is directed to a non-transitory computer
readable medium storing instructions that cause the processor to perform the
same executing, computing, and selecting steps recited in claim 1. Claim 20
is directed to a computing device comprising a memory and a processor
coupled to the memory configured to execute the same executing,
computing, and selecting steps of claim 1.
We agree with the Examiner that under the first step of the Alice
inquiry, each of independent claims 1, 6, and 20 is directed to the abstract
idea of receiving data and employing algorithms to generate, calculate, and
analyze additional data. Our reviewing courts have held claims directed to a
process that employ algorithms in a similar manner, without more, ineligible
under § 101. See Parker v. Flook, 437 U.S. 584, 585, 59A-96 (1978)
(rejecting as ineligible claims directed to (1) measuring the current value for
a variable in a catalytic conversion process, (2) using an algorithm to
calculate an updated “alarm-limit value” for that variable, and (3) updating
the limit with the new value); Digitech Image Techs., LLC v. Elecs. for
Imaging, Inc., 758 F.3d 1344, 1351 (Fed. Cir. 2014) (“Without additional
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limitations, a process that employs mathematical algorithms to manipulate
existing information to generate additional information is not patent
eligible”); Content Extraction, 776 F.3d at 1347-48 (rejecting as ineligible
claims directed to (1) collecting data, 2) recognizing certain data within the
collected data set, and 3) storing that recognized data in a memory); Elec.
Power Grp., LLC v. Alstom S.A., 830 F.3d 1350, 1353—54 (Fed. Cir. 2016)
(discussing how “collecting information” and “analyzing information by
steps people go through in their minds, or by mathematical algorithms,
without more” are abstract ideas). Appellants’ argument that the
“computing” step recited in the claims “necessarily involves generating new
data,” (Reply Br. 5), is of no import because a process that uses
mathematical algorithms to generate additional information from existing
information, without more, is not patent eligible. Digitech, 758 F.3d
at 1351.
Appellant’s argument that the claims are not directed to an abstract
idea because, like the claims at issue in Enfish, the claims are directed to a
specific improvement to computer capabilities is unpersuasive. Reply Br. 3—
5. Appellant admits that the focus of the claims is on improving automated
integrated circuit design processes by “reducing false-positives typically
encountered with conventional automated IC design processes.” Reply
Br. 5. According to Appellant, the improvement is accomplished by
computing a quality score for each output floorplan, and based on the quality
scores, selecting one of the at least one output floorplans for further
execution via at least one automated placement process. Id. at 4. Thus, as
Appellant’s arguments make clear, the claims are directed to an abstract idea
(i.e., using mathematical algorithms to generate, calculate, and analyze
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information) for which a general-purpose computer is involved merely as a
tool instead of on any specific improvement to the functioning or efficiency
of the computer itself.
Turning to the second step of the Alice inquiry, as the Examiner finds,
independent claims 1, 6, and 20 do not contain elements in addition to the
algorithms that transform the nature of the independent claims into patent-
eligible subject matter. Although the method of claim 1 is limited to
designing a floorplan for an integrated circuit, the claim does not recite steps
for manufacturing an integrated circuit. Moreover, attempting to limit the
use of an abstract idea to a particular technological environment does not
render claim 1 patent eligible because the limitation does not transform the
claims into patent-eligible applications of the abstract idea. See Elec.
Power, 830 F.3d at 1354; see also Parker, 437 U.S. at 595 (“If a claim is
directed essentially to a method of calculating, using a mathematical
formula, even if the solution is for a specific purpose, the claimed method is
nonstatutory”).
Claim 6 nominally recites as its subject matter a physical device—a
“non-transitory computer readable medium,” but every substantive
limitation in the body of the claim pertains to the software tools stored in the
medium. Thus, despite its Beauregard format, claim 6 is patent-ineligible
under § 101 for the same reasons as claim 1.
Claim 20 recites a computing device including a memory and a
processor configured to carry out a series of steps that mirror the steps
recited in the method of claim 1, but merely reciting a generic computer
cannot transform a patent-ineligible abstract idea into a patent-eligible
invention. See Mayo, 566 U.S. at 84—85 (“[The Court in Benson] held that
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simply implementing a mathematical principle on a physical machine,
namely a computer, was not a patentable application of that principle.”).
Thus, as with method claim 1, claim 20 is patent-ineligible under § 101 for
the same reasons as claim 1.
Appellant’s pre-emption argument does not alter our view that
independent claims 1, 6, and 20 are properly rejected under § 101. The
extent of pre-emption is a consideration when determining whether a claim
is patent eligible, but the absence of complete pre-emption is not dispositive.
In addition, where claims are determined to disclose patent-ineligible subject
matter under the two-part framework described in Mayo and Alice, pre­
emption concerns are fully addressed and rendered moot. Ariosa
Diagnostics, Inc. v. Sequenom, Inc., 788 F.3d 1371 (Fed. Cir. 2015).
For the foregoing reasons, on this record, we sustain the Examiner’s
rejection of claims 1—20 under 35 U.S.C. § 101.
Rejections 2—4 — Obviousness
We focus our discussion on independent claims 1, 6, and 20, which
include the argued limitations.
The Examiner finds that Gupta discloses or suggests a method of
designing a floorplan for an integrated circuit including all the elements of
claim 1 except “selecting one of the at least one output floorplans for further
execution” based on quality scores. Final Act. 5—6 (citing Gupta Tflf 33, 36,
37, 97, 102, 103; Fig. 9). Specifically, the Examiner finds that: (1) Gupta’s
perturbation/modification of a preliminary primary layout pattern
corresponds to the “executing” step recited in claims 1, 6, and 20, and
(2) Gupta’s cost functions or design metrics corresponds to the “computing”
step recited in claims 1, 6, and 20. Final Act. 5. With regard to the
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“selecting” step recited in claims 1, 6, and 20, the Examiner finds that
Takahashi teaches floorplanning, including looking at a plurality of
floorplan candidates and selecting one for further processing based on a
calculated “evaluation value,” which the Examiner considers as equivalent
to a “quality score.” Final Act. 6 (citing Takahashi 7:40-63). The Examiner
determines that one of ordinary skill in the art would have been led, based on
Takahashi, to look at potential placements or floorplan candidates and select
one of them in Gupta’s method because doing so will allow the method to
find the most optimal floorplan by focusing computation resources on the
better intermediate design. Final Act. 6.
Appellant argued that the Examiner reversibly erred in finding that
Gupta teaches or suggests “executing one or more automated placement
processes ... on one or more seed floorplans to generate at least one output
floorplan” as recited in claims 1, 6, and 20. See Appeal Br. 12—13.
Appellant argues that the teachings of Gupta are directed to the micro­
adjustment of the locations of low-level integrated circuit components in
standard integrated circuit cells, which are employed in floorplanning an
integrated circuit, and therefore, are clearly not equivalent to executing an
automated placement process to generate a floorplan, which involves the
placement of major functional blocks of an integrated circuit. Appeal
Br. 12.
Appellant’s argument is persuasive of reversible error. Appellant’s
Specification discloses that the automated macro placer (AMP) analyzes a
netlist of various elements of the integrated circuit in conjunction with a
floorplan bounding box that represents the integrated circuit die. Spec. 12.
The elements in the netlist include standard cells, such as buffers, inverters,
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AND/NAND/OR gates, as well as larger macros, such as blocks of memory
and other integrated circuit components that can include a hundred or more
standard cells. Id. The AMP attempts to place these elements in an optimal
configuration based on wire length and connectivity to the respective logic
hierarchies associated with each macro. Id. The AMP generally performs
an iterative process that continues until the AMP has converged to a locally
optimal floorplan solution, e.g., when a floorplan solution meets a
predetermined resolution criteria, such as when a weighted composite value
of multiple qualification metrics falls below a target threshold. Id. Thus,
Appellant’s Specification supports Appellant’s argument that although
standard-cells are employed in automated placement processes for
generating floorplans, the placement of objects in a standard-cell layout
design as described in Gupta is not equivalent to “executing one or more
automated placement processes on one or more seed floorplans to generate
at least one output floorplan.”
In response to Appellant’s argument, the Examiner finds that the
placement of objects in a standard cell layout design as disclosed by Gupta’s
Figure 9, and described at 197, includes both the locations of macro blocks
or cells, and the positioning of circuit elements within the cells. Ans. 5. The
Examiner finds that “[tjhis is considered [to be the same as executing one or
more automated placement processes on one or more seed floorplans to
generate] a floorplan [for an integrated circuit] because it contains all of the
same information.” Id. In addition, the Examiner finds that Gupta’s 137
mentioned placement of a cell, and changing positioning of a cell in a
standard-cell layout design. Id. The Examiner finds that generating a
floorplan for an integrated circuit and placement of a cell in a standard-cell
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layout design as disclosed in Gupta are “inter-related” because before a
floorplan is generated, the placement of the cells must be known because as
the positions of cells change, the floorplan has to be changed. See id.
Gupta’s 197 describes the detailed perturbed placement of layout
objects in a standard-cell layout design. According to Gupta, a standard-cell
layout comprises a plurality of features that include a plurality of polysilicon
lines, active-layer shapes, and added features, as well as sub-resolution assist
features (SRAFs) and etch dummies. Gupta 1 5. Gupta’s 197, however,
does not disclose or suggest placing standard cells or macros blocks in a
floorplan for an integrated circuit. Likewise, Gupta’s 137 discloses
changing the position of a cell in a standard-cell layout. Although this may
be “inter-related” to generating a floorplan, on this record, the Examiner has
not established that placing objects in a standard-cell layout design or
changing the position of a cell in a standard-cell layout, as described in
Gupta, is equivalent to “executing one or more automated placement
processes [] on one or more seed floorplans to generate at least one output
floorplan” for an integrated circuit as recited in claims 1, 6, and 20.
Because the Examiner’s rejections all rely on the basic combination of
Gupta and Takahashi, and are based on erroneous factual determinations
(Final Act. 5—11), as discussed above, we cannot sustain any of the stated
obviousness rejections.
DECISION
For the above reasons, the rejection of claims 1—20 under 35 U.S.C.
§ 101 is affirmed, and the rejections of claims 1—20 over Gupta and
Takahashi alone, and further in view of Sinha or Kahng are reversed.
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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