Ex Parte Son et al

Board of Patent Appeals and Interferences

Jun 25, 2009

10886167 (B.P.A.I. Jun. 25, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte YONG-HOON SON, SI-YOUNG CHOI, BYEONG-CHAN LEE,
DEOK-HYUNG LEE, and IN-SOO JUNG
____________

Appeal 2009-001846
Application 10/886,167
Technology Center 2800
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Decided:1 June 25, 2009
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Before KENNETH W. HAIRSTON, JOHN A. JEFFERY,
and CARL W. WHITEHEAD, JR., Administrative Patent Judges.

WHITEHEAD, JR., Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
Appeal 2009-001846
Application 10/886,167

2
Appellants appeal under 35 U.S.C. § 134 from the Examiner’s
rejection of claims 1-9, 33, and 34.2 See App. Br. 3. We have jurisdiction
under 35 U.S.C. § 6(b) (2002). We reverse.

STATEMENT OF THE CASE
Appellants invented a MOS transistor having recessed portions and an
impurity doped epitaxial layer wherein the impurity concentration of the
impurity doped epitaxial layer has a gradient in a vertical direction.3
Claim 1, which further illustrates the invention, follows:
1. A MOS transistor, comprising:
a semiconductor substrate having a first recess and a
second recess therein;
a gate electrode on the semiconductor substrate between
the first recess and the second recess;
a first impurity doped region in the semiconductor
substrate below the first recess;
a second impurity doped region in the semiconductor
substrate below the second recess;
an impurity doped epitaxial layer on the first impurity
doped region and on the second impurity doped region that at
least partially fills the first recess and the second recess; and
a metal silicide layer on the impurity doped epitaxial
layer,
wherein an impurity concentration of the impurity doped
epitaxial layer has a gradient in a vertical direction, and wherein

2 Claim 34 was rejection under 35 U.S.C. § 112, second paragraph in the
Final Rejection mailed October 18, 2006. An amendment filed under 37
C.F.R. § 1.116 amended claim 34 and therefore the Examiner no longer
maintained the rejection. See Advisory Action mailed January 29, 2007.
3 See generally App. Br. 3-4; Spec 2-5.
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a peak impurity concentration of the impurity doped epitaxial
layer is near a top surface of the impurity doped epitaxial layer.

The Rejections
The Examiner relies upon the following prior art reference as
evidence of unpatentability:
Wu US 6,368,926 B1 Apr. 9, 2002
Chau US 6,765,273 B1 Jul. 20, 2004
Sasaki JP 2002-151682 A May 24, 2002
Claims 1-7 stand rejected under 35 U.S.C. § 102(b) as being
unpatentable over Sasaki (Ans. 3-5).
Claim 8 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Sasaki and Wu (Ans. 5-6).
Claims 9, 33, and 34 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Sasaki, Wu, and Chau (Ans. 6-7).
Rather than repeat the arguments of Appellants or the Examiner, we
refer to the Briefs and the Answer for their respective details. In this
decision, we have considered only those arguments actually made by
Appellants. Arguments which Appellants could have made but did not make
in the Briefs have not been considered and are deemed to be waived. See 37
C.F.R. § 41.37(c)(1)(vii) (2008).
Claim 1
Appellants argue that Sasaki discloses epitaxial layers wherein the
peak impurity concentration is near a bottom surface, which is completely
opposite from what is claimed (App. Br. 5). It is the Examiner’s position
that since the claims do not state that the peak impurity concentration is
directly at the top surface, the Examiner is permitted to reasonably interpret
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the claim broadly and therefore claim 1 reads on the Sasaki reference (Ans.
8).

ISSUE
Have Appellants shown that the Examiner erred in finding that Sasaki
discloses a MOS transistor having an epitaxial layer with the peak impurity
concentration is near the top surface of the layer?

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
Sasaki
1. Figures 8a-b of Sasaki are reproduced below:

Figure 8a discloses a MOS transistor having a semiconductor substrate
having a gate electrode (103) on the semiconductor substrate (101),
between the first recess and the second recess, a LDD region (104), first
and second impurity doped regions (107-108) with titanium silicide
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layers (109). Figure 8b discloses the impurity concentration profile of
the device in the cross section along the line 8b-8b.
2. Employing the process disclosed in Figure 8a increases the likelihood of
defects in the source 108/drain 109 or LDD 104 regions as the impurity
concentration profile in the silicon substrate increases (¶ [0007]).
3. Figures 4a-b of Sasaki are reproduced below:

Figure 4a discloses a MOS transistor having a semiconductor substrate
having a gate electrode (13) on the semiconductor substrate, between
the first recess and the second recess, first and second impurity doped
regions (17-18) with impurity doped epitaxial layers (19). Figure 4b
discloses the impurity concentration profile of the device in the cross
section along the line 4b-4b.
4. Sasaki discloses that the impurity concentration peak in the source/drain
regions can be prevented by forming the epitaxial layers on the regions, thus
causing the impurity concentration peak to be formed near the surface or a
deeper location within the regions (¶ [0011]).

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PRINCIPLES OF LAW
Anticipation is established only when a single prior art reference
discloses, expressly or under the principles of inherency, each and every
element of a claimed invention as well as disclosing structure, which is
capable of performing the recited functional limitations. RCA Corp. v.
Applied Digital Data Sys., Inc., 730 F.2d 1440, 1444 (Fed. Cir. 1984); W.L.
Gore & Assocs., Inc. v. Garlock, Inc., 721 F.2d 1540, 1554 (Fed. Cir. 1983).
“[T]he PTO gives claims their ‘broadest reasonable interpretation.’”
In re Bigio, 381 F.3d 1320, 1324 (Fed. Cir. 2004) (quoting In re Hyatt, 211
F.3d 1367, 1372 (Fed. Cir. 2000)). “Moreover, limitations are not to be read
into the claims from the specification.” In re Van Geuns, 988 F.2d 1181,
1184 (Fed. Cir. 1993) (citing In re Zletz, 893 F.2d 319, 321 (Fed. Cir.
1989)).

ANALYSIS
Appellants argue that Sasaki discloses in Figure 4b that the impurity
concentration of each epitaxial layer 19 is at a minimum at the top surface
and increases towards the bottom surface (App. Br. 5). The Examiner does
not disagree with Appellants’ assessment of the Sasaki reference but merely
argues that claim 1 is being broadly interpreted (Ans. 8). It is the
Examiner’s position that since claim 1 states that the peak impurity
concentration is near a top surface as opposed to being directly at the top
surface of the epitaxial layer, claim 1 reads upon the Sasaki reference (Ans.
8).
We agree with Appellants that the Examiner’s interpretation of the
“wherein a peak impurity concentration of the impurity doped epitaxial layer
is near a top surface of the impurity doped epitaxial layer” limitation in
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claim 1 is not a reasonable interpretation. Appellants argue that Sasaki
teaches away from the invention in claim 1 (App. Br. 6). While this
argument is not germane to anticipation, see, e.g., Leggett & Platt, Inc. v.
VUTEk, Inc., 537 F.3d 1349, 1356 (Fed. Cir. 2008) (citation omitted), we
nonetheless find the Examiner’s position untenable.
Sasaki discloses that the problem with the prior art is that the
likelihood of defects in the source 108/drain 109 or LDD 104 regions
increases as the impurity concentration profile in the silicon substrate
increases (FF 1-2). Sasaki attempts to resolve this problem by incorporating
epitaxial layers wherein the peak impurity concentration is near the bottom
surface of the impurity doped epitaxial layers (FF 3-4) (emphasis added).
Sasaki’s resolution is in complete contrast with the invention in claim 1
which requires the peak impurity concentration of the impurity doped
epitaxial layer to be near a top surface of the impurity doped epitaxial layer.
The Examiner does not offer any further explanation to reconcile the
apparent differences between Sasaki and the claimed invention other than
the Examiner’s broad interpretation of the claim limitation (Ans. 8).
We will not sustain the Examiner’s rejection of independent claim 1
and dependent claims 2-7 for similar reasons. Since the other cited
references to Wu and Chau do not cure the deficiencies of Sasaki noted
above with respect to independent claim 1, we will also not sustain the
Examiner’s obviousness rejections of dependent claims 8, 9, 33, and 34 for
similar reasons.

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CONCLUSION
Appellants have shown that the Examiner erred in finding that Sasaki
discloses a MOS transistor having an epitaxial layer with the peak impurity
concentration is near the top surface of the layer.

ORDER
We will not sustain the Examiner’s decision rejecting claims 1-9, 33,
and 34.
REVERSED

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