Ex Parte Skalsky et al

Patent Trial and Appeal Board

Mar 26, 2018

13289311 (P.T.A.B. Mar. 26, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/289,311 11/04/2011
60501 7590 03/28/2018
LENOVO COMPANY (LENOVO-KLS)
c/o Kennedy Lenart Spraggins LLP
301 Congress Avenue
Suite 1350
AUSTIN, TX 78701
FIRST NAMED INVENTOR
Nathan C. Skalsky
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
XRPS9201l0079US 1 8521
EXAMINER
SAIN, GAUTAM
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
03/28/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
office@klspatents.com
kate@klspatents.com
hanna@klspatents.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NATHAN C. SKALSKY and IVAN R. ZAPATA
Appeal 2016-001427
Application 13/289,311 1
Technology Center 2100
Before CARL W. WHITEHEAD JR., JEFFREYS. SMITH
and KAMRAN JIVANI, Administrative Patent Judges.
SMITH, Administrative Patent Judge.
DECISION ON APPEAL
1 Appellants identify Lenovo Enterprise Solutions (Singapore) Pte. Ltd. as
the real party in interest. App. Br. 2.
Appeal 2016-001427
Application 13/289,311
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the rejection of
claims 1, 4--7, 10-13, 16-18, and 20, which are all the claims remaining in
the application. We have jurisdiction under 35 U.S.C. § 6(b ).
We affirm.
Illustrative Claim
1. A method of reliable memory mapping in a computing
system, the computing system including a plurality of memory
modules, the method comprising:
tracking, by a channel mapping module during a testing
phase, test reliability information for each of the plurality of
memory controller address ranges in the computing system;
tracking, by the channel mapping module during run-
time of the computing system, run-time reliability information
for each of the plurality of memory controller address ranges in
the computing system;
determining, by the channel mapping module in
dependence upon the test reliability information and the run-
time reliability information, a reliability rating for each of a
plurality of memory controller address ranges, each memory
controller address range including a distinct range of physical
memory addresses that can be accessed by a distinct memory
controller;
mapping, by the channel mapping module, critical
system-level logical memory addresses to the most reliable
physical memory controller address ranges; and
directing, by the channel mapping module, memory
accesses addressed to a critical system-level logical memory
address to the most reliable physical memory controller address
ranges.
2
Appeal 2016-001427
Application 13/289,311
Pomerantz
Xin
Shalvi
Carnevale
Wood
Wei
Prior Art
US 2007 /0050543 Al
US 7,580,956 Bl
US 2010/0115376 Al
US 2010/0174955 Al
US 2012/0203951 Al
US 2012/0272038 Al
Examiner's Rejections
Mar. 1, 2007
Aug.25,2009
May 6, 2010
July 8, 2010
Aug. 9, 2012
Oct. 25, 2012
Claims 1, 4--7, 10-13, 16-18, and 20 stand rejected under 35 U.S.C.
§ 112, first paragraph, as failing to comply with the written description
requirement.
Claims 1, 4, 6, 7, 10, 12, 13, 16, 18, and20 stand rejected under
35 U.S.C. § 103(a) as unpatentable over Xin, Pomerantz, Wei, Wood, and
Shalvi.
Claims 5, 11, and 17 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Xin, Pomerantz, Wei, Wood, Shalvi, and Carnevale.
ANALYSIS
Section 112 rejection of claims 1, 4-7, 10-13, 16-18, and 20
The Examiner finds that "testing," "run-time," "channel mapping,"
and "physical memory addresses that can be accessed by a distinct memory
controller" as recited in each of independent claims 1, 7, and 13 lack written
description support in the Specification as originally filed. Final Act. 2-3.
Appellants contend that written description support for the claimed
"testing phase" and "channel mapping" is found on page 10, lines 6-17 of
the Specification as originally filed. App. Br. 6. Appellants contend that
written description support for the claimed "run-time phase" is found on
3
Appeal 2016-001427
Application 13/289,311
page 10, lines 19-30 of the Specification as originally filed. Id. at 6-7.
Appellants contend that written description support for the claimed "physical
memory addresses that can be accessed by a distinct memory controller" is
found on page 8, line 19 to page 9, line 7 of the Specification as originally
filed. Id. at 7. The Examiner does not respond in the Answer to Appellants'
contentions.
Having reviewed the cited portions of the Specification, we agree with
Appellants that the cited portions adequately support the claim terms at
issue. Id. at 6-7. Accordingly, we do not sustain the rejection of claims 1,
4--7, 10-13, 16-18, and 20 under 35 U.S.C. § 112, first paragraph.
Section 103 rejection of claims 1, 4, 6, 7, 10, 12, 13, 16, 18, and 20
Claim 1 recites "determining, by the channel mapping module in
dependence upon the test reliability information and the run-time reliability
information, a reliability rating for each of a plurality of memory controller
address ranges." Appellants contend that Xin does not disclose determining
the reliability rating in dependence upon the test reliability information and
the run-time reliability information. App. Br. 8-10. However, the Examiner
relies on Shalvi, not Xin, to teach the dependence upon test reliability
information and run-time reliability information. Final Act. 5 (citing Shalvi
i-fi-1 52, 7 6). In particular, the Examiner finds that Shalvi discloses identifying
defective cells during production testing and during normal operation. Id.
The Examiner finds that the scope of the claimed "run-time reliability
information" encompasses the normal operation of Shalvi. Ans. 11.
In the Reply Brief, Appellants contend for the first time that Shalvi' s
testing identifies defective cells during wafer testing or final package testing,
4
Appeal 2016-001427
Application 13/289,311
not during run-time operation of the system. Reply Br. 12. Appellants'
contention is untimely. See 37 C.F.R. § 41.41(b)(2). Even so, we find
Appellants' contention inconsistent with Shalvi's teaching that "defective
memory cells are identified, during production testing and/ or during normal
operation of the memory." Shalvi i-f 52. Appellants' contention is also
inconsistent with Shalvi' s teaching that the processor "may identify
defective cells during operation of the memory device," and "the identified
defective memory cells may comprise cells that are initially defective, as
well as cells that fail during the lifetime of the memory device." Id. i-f 76.
Appellants further contend that Xin does not disclose the claimed
"determining ... a reliability rating for each of a plurality of memory
controller address ranges." App. Br. 10. According to Appellants, Xin
describes rating the reliability of storage devices, not address ranges. Id.
The Examiner finds that the broadest reasonable interpretation of the
claimed "address ranges," read in light of the Specification, encompasses
memory modules 212, 214 shown in Figure 2 of Appellants' Specification.
Ans. 12. The Examiner further finds that the storage devices of Xin describe
memory modules having "address ranges" within the scope of claim 1. Ans.
11-12.
We agree with the Examiner. Appellants' Specification discloses that
each "memory controller address range may represent, for example, the
entire memory provided by a particular memory module (212, 214) .... "
Spec. 3:21-24. Appellants have not provided persuasive evidence or
argument to distinguish the claimed "reliability rating for each of a plurality
of memory controller address ranges" from the reliability rating assigned to
the storage devices disclosed by Xin.
5
Appeal 2016-001427
Application 13/289,311
Accordingly, we sustain the rejection of claims 1, 4, 6, 7, 10, 12, 13,
16, 18, and 20 under 35 U.S.C. § 103.
Section 103 rejection of claims 5, 11, and 17
Appellants do not present arguments for separate patentability of
claims 5, 11, and 1 7, but rely on those presented for claim 1, which we find
unpersuasive. We, therefore, sustain the rejection of claims 5, 11, and 17
under 35 U.S.C. § 103.
DECISION
The rejection of claims 1, 4--7, 10-13, 16-18, and 20 under 35 U.S.C.
§ 112, first paragraph, as failing to comply with the written description
requirement, is reversed.
The rejection of claims 1, 4, 6, 7, 10, 12, 13, 16, 18, and 20 under
35 U.S.C. § 103(a) as unpatentable over Xin, Pomerantz, Wei, Wood, and
Shalvi is affirmed.
The rejection of claims 5, 11, and 17 under 35 U.S.C. § 103(a) as
unpatentable over Xin, Pomerantz, Wei, Wood, Shalvi, and Carnevale is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).
AFFIRMED
6