Ex Parte Shigenari

Board of Patent Appeals and Interferences

Oct 21, 2009

11093046 (B.P.A.I. Oct. 21, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte TOSHIHIKO SHIGENARI
____________________

Appeal 2009-004285
Application 11/093,0461
Technology Center 2800
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Decided: October 21, 2009
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Before JOHN C. MARTIN, ROBERT E. NAPPI,
and MARC S. HOFF, Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL

1 The real party in interest is Sharp Kabushiki Kaisha.
Appeal 2009-004285
Application 11/093,046

STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from a Final Rejection of
claims 1, 2, and 4-11. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Appellant’s invention relates to a semiconductor device having
electrostatic discharge (ESD) protection circuitry, wherein the
semiconductor device includes a first circuitry including a transistor. A
terminal portion exists for connecting the first circuitry and a second
circuitry to which a predetermined voltage is applied. First protection
sections connect in series between a positive power supply and a negative
power supply. There exists a voltage application section to which a first
voltage is applied. Second protection sections are connected in series
between the voltage application section and the terminal portion (Spec. 7:12-
22).
Claim 6 is exemplary:
6. A semiconductor device, comprising:

a first circuitry including a transistor;

a terminal portion for connecting the first circuitry and a second
circuitry to which a predetermined voltage is applied;

a plurality of first protection sections connected in series between one
of a positive power supply and a negative power supply and a voltage
application section to which a first voltage is applied; and

a plurality of second protection sections connected in series between
the voltage application section and the terminal portion.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
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Ma US 5,982,599 Nov. 9, 1999
Ker US 6,649,944 B2 Nov. 18, 2003
Spehar US 6,693,780 B2 Feb. 17, 2004

Claims 1, 2, 4, and 5 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Ker.
Claims 6-8 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Spehar.
Claim 9 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Spehar.
Claim 10 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Spehar in view of Ma.
Claim 11 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Spehar in view of Ker.
Rather than repeat the arguments of Appellant or the Examiner, we
make reference to the Appeal Brief (filed April 14, 2008), the Reply Brief
(filed August 29, 2008), and the Examiner’s Answer (mailed June 30, 2008)
for their respective details.

ISSUE
Appellant contends that elements D3, D4, D10, and D14 of Spehar are
not punch-through devices (App. Br. 6). Appellant contends that the
modification of the protection circuit of Spehar with the punch-through
devices of Ma would not result in a functional device (App. Br. 8).
The Examiner concludes that it would have been obvious to one of
ordinary skill in the art at the time of the invention was made to modify the
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circuit of Spehar and substitute punch-through devices for the diodes since
Ma discloses that both diodes and punch-through devices may be used to
protect against ESD events (Ans. 8).
Appellant’s contentions present us with the following issue:
Did Appellant show that the Examiner erred in concluding that it
would have been obvious to one of ordinary skill in the art at the time the
invention was made to have substituted punch-through devices for the
diodes of the protection circuit of Spehar, since the teachings of Ma disclose
that either diodes or punch-through devices may be used to protect against
ESD events?

FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
The Invention
1. According to Appellant, the invention concerns a
semiconductor device having ESD protection circuitry, wherein the
semiconductor device includes a first circuitry including a transistor. A
terminal portion exists for connecting the first circuitry and a second
circuitry to which a predetermined voltage is applied. First protection
sections connect in series between a positive power supply and a negative
power supply. There exists a voltage application section to which a first
voltage is applied. Second protection sections are connected in series
between the voltage application section and the terminal portion (Spec. 7:12-
22).
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2. A simple prior art ESD protection circuitry 500 is disclosed that
includes two diodes D51 and D52. A simple prior art ESD protection
circuitry 600 is disclosed that includes punch-through devices P61 and P62
(Figs. 5-6, Spec. 2:20-3:22).
Spehar
3. Spehar teaches in Figure 7 an electrostatic discharge (ESD)
protection circuit for a differential pair of transistors Q1, Q2 including a pair
of bypassing circuits and a clamping circuit. The bypassing circuits include
forward biased diodes D9, D10, D13, and D14 and anti-parallel diodes D5-
D8, D11, and D12 connected between nodes C and D. The clamping
circuits include diode-clamp combination D1-D4 and circuit 12 which
provides protection for ESD events between pad A and VDD or VSS and
between pad B and VDD or VSS of either polarity. Three matching diodes,
BE-1, D10, and D14 are provided to prevent significant diversion of the
input signal through diodes D11, D5, and D6. In a similar manner, BE-2,
D9, and D13 provide the path in the other direction to match the three
parallel diodes D12, D7, and D8. Accordingly, a path of forward biased
diodes from point C to D via BE-1, D10, and D14 allows current to flow
from pad A to pad B which distributes the ESD voltage more uniformly
across BE-1 and BE-2. Without this path, the junctions would eventually be
damaged or destroyed, resulting in a change in the circuit performance (Fig.
4, 6, 7, col. 3, ll. 24-48, col. 4, ll. 34-50).
Ma
4. Ma discloses that a method for preventing damage to integrated
circuit devices from an ESD event is to connect protection devices, such as
diodes or punch-through devices (col. 1, ll. 18-34, col. 5, ll. 59-63).
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PRINCIPLES OF LAW
Anticipation pursuant to 35 U.S.C § 102 is established when a single
prior art reference discloses expressly or under the principles of inherency
each and every limitation of the claimed invention. Atlas Powder Co. v.
IRECO Inc., 190 F.3d 1342, 1347 (Fed. Cir. 1999); In re Paulsen, 30 F.3d
1475, 1478-79 (Fed. Cir. 1994).
Analysis of whether a claim is patentable over the prior art under 35
U.S.C. § 102 begins with a determination of the scope of the claim. We
determine the scope of the claims in patent applications not solely on the
basis of the claim language, but upon giving claims their broadest reasonable
construction in light of the specification as it would be interpreted by one of
ordinary skill in the art. In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359,
1364 (Fed. Cir. 2004). The properly interpreted claim must then be
compared with the prior art.
In an appeal from a rejection for anticipation, Appellant must explain
which limitations are not found in the reference. See Gechter v. Davidson,
116 F.3d 1454, 1460 (Fed. Cir. 1997) ("[W]e expect that the Board's
anticipation analysis be conducted on a limitation by limitation basis, with
specific fact findings for each contested limitation and satisfactory
explanations for such findings.")(emphasis added). See also In re Kahn, 441
F.3d 977, 985-86 (Fed. Cir. 2006).
On the issue of obviousness, the Supreme Court has stated that “the
obviousness analysis cannot be confined by a formalistic conception of the
words teaching, suggestion, and motivation.” KSR Int’l Co. v. Teleflex Inc.,
550 U.S. 398, 419 (2007). Further, the Court stated “[t]he combination of
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familiar elements according to known methods is likely to be obvious when
it does no more than yield predictable results.” Id. at 416. “One of the ways
in which a patent’s subject matter can be proved obvious is by noting that
there existed at the time of the invention a known problem for which there
was an obvious solution encompassed by the patent’s claims.” Id. at 419-
420.
The determination of obviousness must consider, inter alia, whether a
person of ordinary skill in the art would have been motivated to combine the
prior art to achieve the claimed invention and whether there would have
been a reasonable expectation of success in doing so. Brown & Williamson
Tobacco Corp. v. Philip Morris Inc., 229 F.3d 1120, 1125 (Fed. Cir. 2000).
Where the teachings of two or more prior art references conflict, the
Examiner must weigh the power of each reference to suggest solutions to
one of ordinary skill in the art, considering the degree to which one
reference might accurately discredit another. In re Young, 927 F.2d 588,
591 (Fed. Cir. 1991). If the proposed modification would render the prior
art invention being modified unsatisfactory for its intended purpose, then
there is no suggestion or motivation to make the proposed modification. In
re Gordon, 733 F.2d 900, 902 (Fed. Cir. 1984). Further, our reviewing court
has held that “[a] reference may be said to teach away when a person of
ordinary skill, upon reading the reference, would be discouraged from
following the path set out in the reference, or would be led in a direction
divergent from the path that was taken by the applicant.” In re Gurley, 27
F.3d 551, 553 (Fed. Cir. 1994); Para-Ordnance Mfg., Inc. v. SGS Importers
Int’l., Inc., 73 F.3d 1085, 1090 (Fed. Cir. 1995).
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ANALYSIS
Claims 1, 2, 4-9, and 11
Appellant’s notice of appeal dated February 4,2008 states that the
appeal is from the Examiner’s rejection of claims 1, 2, and 4 through 11.
Thus, even though Appellant states on page 3 of the Brief that Appellant is
appealing the rejection of claim 10, the rejection of claims 1, 2, 4 through 9,
and 11 is before us. Appellant has failed to present arguments as to the
rejections of claims 1, 2, 4-9, and 11. Therefore, Appellant has waived any
arguments rebutting the rejection of claims 1, 2, 4-9, and 11. We summarily
sustain the Examiner’s rejection of claims 1, 2, 4-9, and 11 pro forma.
Claim 10
Appellant contends that elements D3, D4, D10, and D14 of Spehar are
not punch-through devices (App. Br. 6). Appellant contends that the
modification of the protection circuit of Spehar with the punch-through
devices of Ma would not result in a functional device (App. Br. 8).
Appellant contends that since diodes and punch-through devices function
differently, the interconnections of the protection circuit of Spehar would
need to change (App. Br. 8).
The Examiner concludes that it would have been obvious to one of
ordinary skill in the art at the time of the invention was made to modify the
circuit of Spehar and substitute punch-through devices for the diodes, since
Ma discloses that both diodes and punch-through devices may be used to
protect against ESD events (Ans. 8, FF 3, 4). The Examiner finds that
Appellant’s argument that the diodes of Spehar are not punch-through
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devices is irrelevant, since the Examiner did not cite Spehar for disclosing
punch-through devices (Ans. 8).
In response to what the Examiner interprets as a bodily incorporation
argument, the Examiner finds that Ma discloses a method for preventing
damage to a circuit from ESD events is to connect diodes or punch-through
devices (Ans. 8, FF 4). The Examiner further finds that the test for
obviousness is not whether the features of a secondary reference may be
bodily incorporated into the structure of the primary reference; nor is it that
the claimed invention must be expressly suggested in any one or all of the
references (Ans. 9). Rather, the test is what the combined teachings of the
references would have suggested to those of ordinary skill in the art. See In
re Keller, 642 F.2d 413 (CCPA 1981) (Ans. 9).
We are not persuaded by Appellant’s arguments. We agree with the
Examiner’s conclusion that it would have been obvious to one of ordinary
skill in the art at the time of the invention was made to modify the circuit of
Spehar by substituting the diodes with the punch-through devices taught in
Ma. Further support for the Examiner’s conclusion of obviousness is found
in the Background section of the Appellant’s Specification. In particular,
Appellant discloses a prior art ESD protection circuitry 500 that includes
two diodes D51 and D52 and a prior art ESD protection circuitry 600 that
includes punch-through devices P61 and P62 (FF 2). Although the punch-
through devices P61 and P62 are not simply substituted for diodes D51 and
D52, it would have been recognized by those skilled in the art that an
alternative embodiment of the protection circuitry of Spehar would include
punch-through devices in an arrangement that performs the ESD protection
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function of forward biased diodes D9, D10, D13, and D14 and clamping
circuits including diodes D1-D4 (FF 3, 4).
We therefore find no error in the Examiner’s rejection of claim 10
under 35 U.S.C. § 103.

CONCLUSIONS OF LAW
Appellant has not shown that the Examiner erred in concluding that it
would have been obvious to one of ordinary skill in the art at the time the
invention was made to have substituted punch-through devices for the
diodes of the protection circuit of Spehar, since the teachings of Ma disclose
that either diodes or punch-through devices may be used to protect against
ESD events.

ORDER
The Examiner’s rejection of claims 1, 2, and 4-11 is affirmed.
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD

HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON, VA 20195

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