Ex Parte Shen et al

Patent Trial and Appeal Board

Aug 22, 2016

13303863 (P.T.A.B. Aug. 22, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/303,863 11/23/2011
127614 7590 08/24/2016
Wong & Rees LLP
4677 Old Ironsides Drive, Suite 370
Santa Clara, CA 95054
FIRST NAMED INVENTOR
Jingying Shen
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
70063-0028 1172
EXAMINER
ALROBAIE, KHAMDAN N
ART UNIT PAPER NUMBER
2824
NOTIFICATION DATE DELIVERY MODE
08/24/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@wongrees.com
jyang@wongrees.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Exparte
JINGYING SHEN, ROBERT TOWER FREY, KELVIN MARINO, and
JOSHUA HARRIS BROOKS
Appeal2015-003945
Application 13/303,863
Technology Center 2800
Before LINDA M. GAUDETTE, JAMES C. HOUSEL, and
MICHELLE N. ANKENBRAND, Administrative Patent Judges.
GAUDETTE, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2015-003945
Application 13/303,863
Appellants1 appeal under 35 U.S.C. § 134(a) from the Examiner's decision2
finally rejecting claims 1-9 and 11-19 under 35 U.S.C. § 103(a) as unpatentable
over Sweere et al. (US 2010/0008175 Al, published Jan. 14, 2010 ("Sweere")) in
view ofKonstadinidis et al. (US 2010/0229021 Al, published Sept. 9, 2010
("Konstadinidis")), and claims 10 and 20 under 35 U.S.C. § 103(a) as unpatentable
over the same references, further in view of Zimmermann et al. (US 6,816,428 B2,
issued Nov. 9, 2004 ("Zimmermann")). We have jurisdiction under 35 U.S.C.
§ 6(b ).
We AFFIRM.
The invention relates to "a memory management system, and more
particularly to a system for providing power to a dual in-line memory module."
Specification filed November 23, 2011 ("Spec.") i-f 1. Of the appealed claims,
claims 1, 6, and 11 are independent. Claim 1 is representative of the invention and
reads as follows:
1. A method of manufacture of a memory management system
compnsmg:
fabricating a dual in-line memory module carrier;
mounting a volatile memory device on the dual in-line memory
module carrier;
mounting a non-volatile memory on the dual in-line memory
module carrier on a side opposite the volatile memory device;
mounting an uninterruptible power supply on the dual in-line
memory module carrier for maintaining a memory module power
when a system power input decays, wherein the memory module
power is reduced by no more than 20 millivolts (m V) during a
1 Appellants identify the real party in interest as SMART Modular Technologies,
Inc. Appeal Brief filed October 6, 2014 ("App. Br."), 3.
2 Final Office Action mailed June 5, 2014 ("Final Act.").
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Application 13/303,863
transition time when the memory module power is transitioned
between a system power source and a back-up power source; and
mounting a controller logic integrated circuit on the dual in-line
memory module carrier coupled to the volatile memory device, the
non-volatile memory, and the uninterruptible power supply for
copying data content of the volatile memory device to the non-volatile
memory when the uninterruptible power supply detects the decay of
the system power input to a first cross-over level.
App. Br. 17 (Claims Appendix).
The Examiner finds Sweere discloses a method and system as claimed,
including the capability of transitioning between system and back-up power
sources when the memory module is reduced by a threshold voltage, but "is silent
in teaching the detected voltage during the transition to be no more than 20
millivolts (mV)." Final Act. 3 (as to claim 1); see also id. at 4--7 (regarding claims
6 and 11 ). The Examiner finds Konstadinidis discloses a system that includes a
memory device, and monitors supply voltage. Id. at 3 (citing Konstadinidis i-f 22).
The Examiner finds Konstadinidis teaches detecting a threshold voltage drop of 20
mV. Id. The Examiner further finds that, based on Konstandinidis' teaching, one
of ordinary skill in the art at the time of the invention would have been motivated
"to limit the power supply voltage drop for [Sweere' s] memory device in order to
maintain the data integrity and prevent lo[]sing data due to insufficient power
supply." Id. at 3--4 (as to claim 1); see also id. at 5-7 (regarding claims 6 and 11).
Appellants expressly state that "claims 2-5, 7-[10], and 12-[20] ... stand or
fall with independent claims 1, 6, or 11, from which they depend." App. Br. 14--
15; see also Reply Brief filed January 30, 2015 ("Reply Br."), 6-7. Appellants'
arguments in support of patentability as to all appealed claims are based on their
contention that Sweere and Konstadinidis, alone or in combination, fail to disclose
or suggest "an uninterruptible power supply ... for maintaining a memory module
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Application 13/303,863
power ... wherein the memory module power is reduced by no more than 20
millivolts (m V)" as recited in each of independent claims 1, 6, and 11. App. Br.
12; see generally id. at 12-15. Appellants argue, more specifically, that
Konstadinidis detects a voltage drop of "20 m V or more" (Konstadinidis i-f 22),
whereas the claims recite that "memory module power is reduced by no more than
20 mV" (claims 1, 6, and 11). Id. at 13.
Konstandinidis relates to a voltage drop monitoring and correcting circuit for
a microprocessor that performs a temporary clock-skipping technique to
compensate for voltage drops. Konstandinidis i-f 7. Konstandinidis discloses that
when a voltage drop of, "e.g., ... 20 m V or more is detected," the microprocessor
clock is temporarily stopped to allow the supply voltage to recover to its normal
level. Id. i-f 22. According to Konstandinidis, one advantage of the invention is
that "notwithstanding changes in supply current, supply voltage of a
microprocessor can be maintained at a steady level." Id. i-f 34.
A prima facie case of obviousness exists where the prior art and claimed
ranges overlap, as well as in those cases where the claimed range and the prior art
range, though not overlapping, are sufficiently close that one skilled in the art
would have expected them to have the same properties. In re Peterson, 315 F .3d
1325, 1329 (Fed. Cir. 2003). In the present case, Konstandinidis' voltage drop
range (20 m V or more) and Appellants' claimed range (no more than 20 m V)
overlap at their respective low and high points, i.e., 20 m V. Therefore, the relevant
case law supports the Examiner's determination that the claimed invention would
have been obvious over the combination of Sweere and Konstandinidis.
Appellants argue the recited range of "no more than 20 m V" is critical,
contending "memory module power reduced by no more than 20 m V has been
discovered to provide improved reliability for memory management systems. The
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Appeal2015-003945
Application 13/303,863
improved reliability is provided because the memory module power provides no
operational loss of energy for the total memory back-up process of the memory
management systems." App. Br. 14; Reply Br. 6. Appellants contend paragraphs
40-41 of the Specification provide evidence of unexpected results. Id.
"[W]hen unexpected results are used as evidence of nonobviousness, the
results must be shown to be unexpected compared with the closest prior art." In re
Baxter Travenol Labs., 952 F.2d 388, 392 (Fed. Cir. 1991). We have reviewed
paragraphs 40 and 41 of the Specification, but do not find the statements made
therein constitute persuasive evidence of nonobviousness. For example, there is no
showing that operational loss of energy would occur to the memory management
system if memory module power were reduced by more than 20 m V. "A strong
case of prima facie obviousness, such as that presented here, cannot be overcome
by a far weaker showing of objective indicia of nonobviousness." Takai Corp. v.
Easton Enters., Inc., 632 F.3d 1358, 1371 (Fed. Cir. 2011).
In their Reply Brief, Appellants argue for the first time on appeal that
"Konstadinidis teaches away from Sweere by showing that when the low voltage
or voltage [drop] event occurs, the clock must be disabled which would render the
Sweere memory module inoperative." Reply Br. 5. "Properly interpreted, the
Rules do not require the Board to take up a belated argument that has not been
addressed by the Examiner, absent a showing of good cause." Ex parte Borden, 93
USPQ2d 1473, 1477 (Bd. Pat. App. & Int. 2010) (informative). We have
considered, however, but do not find persuasive this argument as it fails to show
error in the facts and reasons relied on by the Examiner in rejecting the claims.
The Examiner's rejection is not based on employing Konstadinidis' system of
disabling the clock in Sweere' s system. See Reply Br. 5 ("Therefore, the
combination of the Konstadinidis clock for the Sweere memory module would
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Appeal2015-003945
Application 13/303,863
teach an inoperative Sweere memory module because the memory module cannot
operate when the clock is disabled."). Rather the Examiner relies on
Konstandinidis solely for a teaching of a suitable voltage drop for transitioning
between system and back-up power sources in Sweere's system. See Final Act. 3-
4.
In sum, for the reasons stated in the Final Office Action, the Examiner's
Answer, and above, we find a preponderance of the evidence, taking into account
Appellants' evidence of unexpected results, favors the Examiner's conclusion of
obviousness as to claims 1-20.
No time period for taking any subsequent action in connection with this
appeal maybe extended under 37 C.F.R. §1.136(a)(l)(iv).
AFFIRMED
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