Ex Parte SHEN et al

Patent Trial and Appeal Board

Jul 17, 2018

14949423 (P.T.A.B. Jul. 17, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/949,423 11/23/2015
110506 7590 07/19/2018
Patent Capital Group - Analog
Attn: Bonnie Boyle
4524 Briar Hollow Drive
Plano, TX 75093
FIRST NAMED INVENTOR
JUNHUASHEN
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
26256.0371-NP
(APD5441-l)
9551
EXAMINER
NGUYEN, LINH V
ART UNIT PAPER NUMBER
2845
NOTIFICATION DATE DELIVERY MODE
07/19/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
bonnie@patcapgroup.com
P AIR_l 10506@patcapgroup.com
eofficeaction@appcoll.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JUNHUA SHEN, MARK D. MADDOX, and
RONALD ALAN KAPUSTA
Appeal2017-008536
Applicationl4/949,423 1
Technology Center 2800
Before JEFFREY T. SMITH, N. WHITNEY WILSON, and
BRIAND. RANGE, Administrative Patent Judges.
RANGE, Administrative Patent Judge.
DECISION ON APPEAL
SUMMARY
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's
decision rejecting claims 1-6 and 8-19. We have jurisdiction under
35 U.S.C. § 6(b ).
We AFFIRM-IN-PART.
1 Appellant is the Applicant, Analog Devices, Inc., which according to the
Appeal Brief, is also the real party in interest. Appeal Br. 4.
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Application 14/949,423
STATEMENT OF THE CASE2
Appellant describes the invention as relating to a circuit design for
successive-approximation register analog-to-digital converters. Spec. ,r 1.
Claims 1 and 14, reproduced below with formatting added for readability
and emphases added to certain key recitations, is illustrative of the claimed
subject matter:
1. A successive approximation register analog-to-digital
converter (SAR ADC), the SAR ADC comprising:
a plurality of capacitive digital-to-analog converter
(DAC) units corresponding to a plurality of bit trials,
wherein each capacitive DAC unit comprises:
and
bit capacitors corresponding to a particular
bit weight, for directly sampling the analog
input and generating outputs of the capacitive
DAC unit;
an on-chip reference capacitor dedicated
to the bit capacitors, for pulling a reference
charge from a reference voltage; and
switches to connect plates of the on-chip
reference capacitor to respective bit
capacitors to provide the reference charge to
the bit capacitors during a conversion phase;
a comparator coupled to the outputs of the
capacitive DAC units for generating a decision output for
each bit trial.
14. A method for converting an analog input to a digital output, and
the method comprises:
tracking and sampling the analog input by one or more bit
capacitors;
2 In this Decision, we refer to the Final Office Action dated August 15, 2016
("Final Act."), the Appeal Brief filed January 9, 2017 ("Appeal Br."), the
Examiner's Answer dated March 23, 2017 ("Ans."), and the Reply Brief
filed May 22, 2017 ("Reply Br.").
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Application 14/949,423
charging an on-chip reference capacitor dedicated to the
one or more bit capacitors by coupling the on-chip reference
capacitor to a reference voltage;
disconnecting the on-chip reference capacitor from the
reference voltage; and
closing switches to connect the on-chip reference capacitor
disconnected from the reference voltage to the one or more bit
capacitors to provide a reference charge for the one or more bit
capacitors to make a bit decision.
Appeal Br. 22, 25 (Claims App., emphases added).
REFERENCES
The Examiner relies upon the prior art below in rejecting the claims
on appeal:
Kapusta
Shen et al.
("Shen")
US 2012/0242523 Al
US 2014/0266847 Al
REJECTIONS
Sept. 27, 2012
Sept. 18, 2014
The Examiner maintains the following rejections on appeal:
Rejection 1. Claims 14--18 under 35 U.S.C. § 102 as anticipated by
Shen. Ans. 2.
Rejection 2. Claims 1---6, 8, 12, 13, and 19 under 35 U.S.C. § 103 as
unpatentable over Shen in view of Kapusta. Id.
Rejection 3. Claims 9-11 under 35 U.S.C. § 103 as unpatentable over
Shen combined with Kapusta and further in view of Haneda. Id.
In the Answer, the Examiner withdraws the 35 U.S.C. § 103 rejections
of claims 7 and 20. Id. at 2-3.
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ANALYSIS
We review the appealed rejections for error based upon the issues
identified by Appellant and in light of the arguments and evidence produced
thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential),
cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) ("[I]t
has long been the Board's practice to require an applicant to identify the
alleged error in the examiner's rejections."). After considering the evidence
presented in this Appeal and each of Appellant's arguments, we are not
persuaded that Appellant identifies reversible error except where otherwise
explained below. Thus, where we affirm the Examiner's rejections (i.e.,
claims other than claim 15), we do so for the reasons expressed in the Final
Office Action and the Answer. We add the following primarily for emphasis.
Rejection 1, claims 14, 16-18. The Examiner rejects claims 14--18
under 35 U.S.C. § 102 as anticipated by Shen. Ans. 2. Appellant presents
separate arguments for claims 14 and 15. We limit our discussion to those
claims. Claims 16-18 will stand or fall with claim 14, from which they
depend.
The Examiner finds that Shen teaches a method of converting an
analog input to a digital output as recited by claim 14. Final Act. 2-3 ( citing
Shen). In particular, the Examiner finds that Shen's on-chip reference
capacitor 614 is dedicated to the one or more bit capacitors 616.1 and 616.2.
Id. at 2. The Examiner also finds that Shen's Figure 6 denotes that Shen's
circuitry is "included in a single integrated circuit." Ans. 6-7.
Appellant argues that Shen's capacitor 614 is not "dedicated to the
one or more bit capacitors," as recited in claim 14. Appeal Br. 13. In
particular, Appellant argues that capacitor 614 is "shared with sampling
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Application 14/949,423
capacitors for making many bit decisions." Id. Claim 14, however, permits
the reference capacitor to be dedicated to "one or more bit capacitors"
( emphasis added) and provides no upper limit to the number of bit capacitors
the reference capacitor may be dedicated to. Similarly, Appellant's
Specification indicates that the reference capacitor can share a charge with
"at least one bit capacitor" and merely identifies a preference for the
reference capacitor being dedicated to only a pair of bit capacitors.
Spec. ,r 69.
Appellant cites paragraphs 22, 32, and 38 of Shen to try to establish
that Shen teaches one reservoir capacitor being shared with sampling
capacitors. Appeal Br. 13. Appellant, however, does not persuasively
explain how these paragraphs teach this point or how this point distinguishes
the language of claim 14 from the teachings of Shen including, for example,
Shen Figure 6. Accordingly, Appellant's argument concerning a dedicated
reference capacitor does not identify reversible error.
Appellant also argues that Shen does not explicitly or implicitly teach
that capacitor 614 is "on-chip." Appeal Br. 14. The Examiner, however,
finds that Figure 6 of Shen indicates that capacitor 614 is "on-chip" (i.e.,
included on the same semiconductor substrate / same integrated circuit as the
SAR ADC). Ans. 6-7. Appellant does not explain why the Examiner's
finding regarding Figure 6 of Shen is incorrect but instead only states in a
conclusory fashion that "Shen does not explicitly or implicitly suggest that
Cres 614 is on-chip." Reply Br. 2.
Moreover, Kapusta includes similar figures to Shen Figure 6 (see,
e.g., Kapusta Fig. 4, 5) and expressly teaches that its apparatus is part of an
integrated circuit chip (Kapusta ,r,r 1, 19). Kapusta thus supports the
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Examiner's position that Figure 6 of Shen indicates on-chip components.
Appellant's argument therefore does not identify reversible error, and we
sustain the Examiner's rejection of claims 14 and 16-18.
Rejection 1, claim 15. The Examiner also rejects claim 15 under 35
U.S.C. § 102 as anticipated by Shen. Ans. 2. Claim 15 recites:
15. The method of Claim 14, wherein:
the one or more bit capacitors comprises a pair of bit
capacitors; and
the method further comprises differentially shorting first
plates of the pair of bit capacitors to settle to a common mode
voltage prior to the on-chip reference capacitor providing the
reference charge to the pair of bit capacitors.
Appeal Br. 25 (Claim App.).
Appellant argues that Shen does not teach differentially shorting
plates of the pair of capacitors to a common mode voltage. Appeal Br. 14--
15. Such a short is depicted by Appellant's Specification as short 3208 at
Figure 32. Spec. ,r 66.
We understand the Examiner's position as maintaining that that this
aspect of claim 15 is met by bit capacitors of Shen each settling to common
ground mode voltage. Ans. 7-8 ( citing Shen Fig. 6). We agree with the
Appellant, however, that a ground voltage is not the same as a common
mode voltage recited by claim 15. Reply Br. 2. Rather, claim 15 recites
capacitors settling to a "common mode voltage" which, given the context of
the Specification, is best understood as an operational voltage rather than
merely being ground voltage. Spec. ,r 73 ( explaining that closing switch
3208 results in capacitors "differentially shorted to settle to a common mode
voltage ( of the sampled input signal in the bit capacitors)"). Because the
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Examiner has not adequately explained how Shen teaches all recitations of
claim 15, we do not sustain the Examiner's rejection of this claim.
Rejections 2 and 3. The Examiner rejects claims 1---6, 8, 12, 13, and
19 under 35 U.S.C. § 103 as unpatentable over Shen in view ofKapusta and
rejects claims 9-11 under 35 U.S.C. § 103 as unpatentable over Shen
combined with Kapusta and further in view ofHaneda. Ans. 2.
Appellant argues these rejections and these claims as a group. See
Appeal Br. 15-19. Therefore, consistent with the provisions of 3 7 C.F .R.
§ 4I.37(c)(1)(iv)(2013), we limit our discussion to claim 1, and all other
claims on appeal stand or fall together with claim 1.
The Examiner finds that Shen teaches most recitations of claim 1.
Final Act. 5 ( citing Shen). In this regard, the analysis is similar to the
analysis of claim 14. The Examiner finds that Shen does not disclose a
plurality of capacitive digital-to-analog converter units. Final Act. 5. The
Examiner finds, however, that Kapusta teaches such a structure. The
Examiner concludes that it would have been obvious to employ this aspect
of Kapusta with Shen "for the purpose of improv[ing] the speed at which the
charge redistribution DAC settles, in particular[,] for a SAR ADC
application." Final Act. 6.
Appellant again argues that Shen lacks a dedicated on-chip reference
capacitor. Appeal Br. 16. For the reasons explained above with regard to
claim 14, this argument does not identify reversible error.
Appellant argues that the Examiner's stated rationale for combining
the references is technically inaccurate. Appeal Br. 16-17. In particular,
Appellant states that combining the references would not improve speed. Id.
at 17. Appellant presents no evidence, however, to support this position.
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Moreover, Kapusta indicates that its arrangement improves speed. Kapusta
,r 5; see also Ans. 13. Thus, the preponderance of the evidence of record
supports the Examiner's position.
Appellant also argues that Kapusta teaches away from directly
sampling analog input. Appellant, however, does not persuasively explain
how Kapusta criticizes, discredit, or otherwise discourage the Examiner's
proposed combination. See, e.g., In re Fulton, 391 F.3d 1195, 1201 (Fed.
Cir. 2004) ("The prior art's mere disclosure of more than one alternative
does not constitute a teaching away from any of these alternatives because
such disclosure does not criticize, discredit, or otherwise discourage the
solution claimed in the' 198 application."). Appellant argues that Kapusta is
different than claim 1 because it does not directly sample analog input, but
this argument does not address the primary reference Shen or the Examiner's
proposed combination. "Non-obviousness cannot be established by
attacking references individually where the rejection is based upon the
teachings of a combination of references." In re Merck & Co., 800 F.2d
1091, 1097 (Fed. Cir. 1986). Appellant's argument therefore does not
establish reversible error.
Finally, Appellant argues that the combining the teachings of Shen
and Kapusta would be unpredictable. The preponderance of the evidence,
however, supports that the Shen and Kapusta devices are similar. Final
Act. 6. This similarity suggests that there would be a reasonable expectation
of success in modifying the Shen devices so that it includes a plurality of
DAC (digital-to-analog converter) units. Ans. 16. Cf, e.g., PAR Pharm.,
Inc. v. TWI Pharms., Inc., 773 F.3d 1186, 1198 (Fed. Cir. 2014). ("The
reasonable expectation of success requirement for obviousness does not
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necessitate an absolute certainty for success."). Appellant states that such a
combination is "counter-intuitive," but Appellant does not persuasively
explain how the evidence supports that a reasonable expectation of success
in the proposed combination is lacking.
Because Appellant does not identify reversible error, we sustain these
rejections.
DECISION
For the above reasons, we affirm the Examiner's rejections (a) of
claims 14 and 16-18 under 35 U.S.C. § 102 as anticipated by Shen, (b) of
claims 1---6, 8, 12, 13, and 19 under 35 U.S.C. § 103 as unpatentable over
Shen in view ofKapusta, and (c) of claims 9-11 under 35 U.S.C. § 103 as
unpatentable over Shen combined with Kapusta and further in view of
Haneda. We reverse the Examiner's rejection (d) of claim 15 under 35
U.S.C. § 102 as anticipated by Shen.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED-IN-PART
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