Ex Parte Shaw

Board of Patent Appeals and Interferences

Mar 27, 2012

11138005 (B.P.A.I. Mar. 27, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte MARK SHAW
____________

Appeal 2009-013330
Application 11/138,005
Technology Center 2100
____________

Before JOHN A. JEFFERY, ELENI MANTIS MERCADER, and DENISE
M. POTHIER, Administrative Patent Judges.

POTHIER, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2009-013330
Application 11/138,005

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STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 7-10, 12-17, 19, and 20. Claims 1-6, 11, and 18 have
been canceled. App. Br. 2. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

Invention
Appellant’s invention relates to a system for detecting subsystem
installation defects. See Abstract. Claim 7 is reproduced below with a key
disputed limitation emphasized:
7. A system for detecting a memory card installation defect,
comprising:

a detection tool configured to be implemented in a system having
at least one memory card with a memory coupled to a processor via a
bus, wherein the bus comprises at least one control line employed to
control an operation of the memory on the memory card, the detection
tool comprising:

logic that generates a test value to be applied to the memory
card over the bus through a plurality of interconnects;

logic that generates a first parity bit for the test value;

logic that transmits the test value to the memory card over the
bus through the interconnects, wherein at least a portion of the test
value is transmitted to the memory card over the control lines; and

logic that compares the first parity bit with a second parity bit
to determine if a fault exists in one of the interconnects, wherein
the second parity bit is generated for the test value in the memory
card.

Appeal 2009-013330
Application 11/138,005

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The Examiner relies on the following as evidence of unpatentability:
Quatse US 4,864,531 Sept. 5, 1989
Byers US 4,962,501 Oct. 9, 1990
Christie US 5,835,511 Nov. 10, 1998
Frankowsky US 6,961,880 B2 Nov. 1, 2005
(filed July 30, 2001)

THE REJECTIONS
1. Claims 7, 8, 12-15, 19, and 20 are rejected under 35 U.S.C.
§ 103(a) as unpatentable over Christie and Byers. Ans. 3-6.1
2. Claims 9 and 16 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Christie, Byers, and Quatse. Ans. 6-7.
3. Claims 10 and 17 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Christie, Byers, and Frankowsky. Ans. 7-8.

THE OBVIOUSNESS REJECTION OVER CHRISTIE AND BYERS
Regarding independent claim 7, the Examiner finds that Christie
discloses and teaches all the limitations, except for using memory cards. See
Ans. 4-5. The Examiner cites to Byers to teach using memory cards and to
modify Christie based on this teaching. See Ans. 5.
Among other arguments, Appellant asserts that Christie does not teach
or suggest that the second parity is generated from the test value in the
memory card 108 but rather is generated in the peripheral 104. App. Br. 7-8.

1 Throughout this opinion, we refer to (1) the Appeal Brief filed January 13,
2009; (2) the Examiner’s Answer mailed April 17, 2009; and (3) the Reply
Brief filed May 11, 2009.
Appeal 2009-013330
Application 11/138,005

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ISSUE
Under § 103, has the Examiner erred in rejecting claim 7 by finding
that Christie and Byers collectively would have taught or suggested the
second parity bit is generated for the test value in the memory card?

FINDINGS OF FACT (FF)
1. We adopt the Appellant’s findings quoting from Christie. See
App. Br. 6-7 (quoting Christie, col. 2, l. 66 – col. 3, l. 35).
2. Christie states the processor 102 transfers data to the peripheral
104 using data bus 114 and control bus 118. Col. 3, ll. 10-14; Fig. 1.
3. Christie states parity generator 110 generates the parity of the data
to be transferred. The parity signal is transferred to peripheral 104 using
parity line 120. Col. 3, ll. 15-23; Fig. 1.
4. Christie also discloses peripheral device 104 has a parity checker
112 that recalculates the parity of the transferred data depending on the
control signal transfers from the control bus 118. The checker compares the
calculated parity with the original parity generated by parity generator 110.
Col. 3, ll. 24-34; Fig. 1.

ANALYSIS
Based on the record before us, we find error in the Examiner’s
obviousness rejection of claim 7, which recites the second parity bit is
generated for the test value in the memory card. We agree with Appellant
that Christie’s peripheral unit 104: (1) compares the first parity bit with a
second parity and (2) generates the second parity bit when recalculating the
parity. See FF 1-4. As the second parity bit is generated in the peripheral
Appeal 2009-013330
Application 11/138,005

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device (i.e., 104) and not the memory (i.e., 108), which is proposed to be a
memory card when combined with Byers’ teaching (see Ans. 5), Christie
fails to teach logic that compares the first parity bit with a second parity bit,
whereby the second parity bit is generated for the test value in the memory
card.
In the Response to Arguments’ section of the Answer, however, the
Examiner asserts that this limitation is met by combining Byers’ teaching of
an error/fault detection logic, such as a parity checker, presumably
embedded in a memory card with Christie. See Ans. 8-9 (citing to Byers,
col. 4, ll. 60-61). The Examiner’s position is that Byers teaches drawing “a
box around Memory 108 and peripheral 104 in Figure 1 of Christie and
label[ing] the box as a card, hence; [sic] the combination of Christie and
Byers et al. teach[es] each and every limitation in claims 7 and 14.” Ans. 9.
This position is problematic for several reasons. Column 4, lines 60-
61 in Byers describe “card fault detecting logic (not shown).” Relying on
this statement alone, Byers does not explicitly state that logic is part of the
card or embedded in the memory card. See Reply Br. 3. While the term,
“card,” in front of the phrase, “fault detecting logic,” may suggest the logic
is part of a card, Byers states that the logic is not shown. See Byers, col. 4,
ll. 60-61. Thus, we cannot be certain, based on this statement alone in
Byers, where the described fault detecting logic is actually located and thus
whether the second parity can be generated for the test value in the memory
card.
Yet, even more troubling, is that this new discussion of Byers and the
citation to column 4 represents a clear shift in the Examiner’s position
between that articulated in the rejection. Compare Ans. 5 with Ans. 8-9.
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Application 11/138,005

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Originally and citing to column 1, the Examiner relied upon Byers for using
memory cards. See Ans. 5. Now, the Examiner asserts Byers teaches parity
checkers or logic being embedded in a memory card. Ans. 9. Such shifts
run counter to the notions of fundamental fairness in an appellate
proceeding. That is, this appeal was taken based on the Examiner’s position
articulated in the rejection and not the Response to Arguments’ section. See
37 C.F.R. § 41.31. To the extent the Examiner decided to abandon the
position in the rejection in favor of another on appeal, such a shift must be
designated as a new ground of rejection – a procedural requirement not
followed here. See MPEP 1207.03; see In re Kumar, 418 F.3d 1361, 1368
(Fed. Cir. 2005).
Although Appellant did not petition this procedural inconsistency (see
Reply Br. 2-4), we are presented with two different positions in the
Examiner’s Answer. We decline to reach the merits of the newer position
because this posture varies from the rejection from which the appeal was
taken.2 Nonetheless, we find both positions problematic for the
above-noted reasons.
For the foregoing reasons, Appellant has persuaded us of error in the
rejection of: (1) independent claim 7; (2) independent claim 14 which recites
commensurate limitations; and (3) dependent claims 8, 12, 13, 15, 19, and
20 for similar reasons.

2 The Board reviews the Examiner’s final rejection in appeals under 35
U.S.C. § 134(a). See In re Webb, 916 F.2d 1553, 1556 (Fed. Cir. 1990).
Appeal 2009-013330
Application 11/138,005

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THE REMAINING OBVIOUSNESS REJECTIONS
Claims 9, 10, 16, and 17 depend from independent claims 7 and 14.
The Examiner has not relied on Quatse or Frankowsky to cure the
above-noted deficiencies of claims 7 and 14. See Ans. 6-8. Thus, because
we reverse the Examiner’s rejection of independent claims 7 and 14, we
likewise will not sustain the rejections of claims 9, 10, 16, and 17.

CONCLUSION
The Examiner erred in rejecting claims 7-10, 12-17, 19, and 20 under
§ 103.

DECISION
The Examiner’s decision rejecting claims 7-10, 12-17, 19, and 20 is
reversed.

REVERSED

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