Ex Parte Shastri et al

Board of Patent Appeals and Interferences

Jan 13, 2009

11346718 (B.P.A.I. Jan. 13, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte KALPENDU SHASTRI,
VIPULKUMAR PATEL,
DAVID PIEDE, and JOHN FANGMAN
____________

Appeal 2008-5375
Application 11/346,718
Technology Center 2800
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Decided: January 13, 2008
____________

Before CHUNG K. PAK, TERRY J. OWENS, and CATHERINE Q. TIMM,
Administrative Patent Judges.

TIMM, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 1, 4, and 5. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm the Examiner’s decision to reject claims 1 and 5. We
reverse the Examiner’s decision to reject claim 4. We enter a new ground of
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rejection for claims 4 and 5 based on our authority under 37 C.F.R. §
41.50(b)(2005).
STATEMENT OF THE CASE
The invention relates to a vertically stacked packaging arrangement
for multiple integrated circuit chips, including SOI-based optical
components, associated electronic integrated circuits, and an optical
input/output (I/O) coupling element. (Spec. ¶¶ 4 and 5). Claims 1, 4, and 5
are illustrative of the subject matter on appeal:
1. A vertically stacked arrangement of a plurality of integrated
circuits, the arrangement comprising:

a silicon-on-insulator (SOI)-based opto-electronic integrated circuit
comprising at least a silicon substrate, an intermediate dielectric layer and a
relatively thin silicon surface layer (SOI layer)

at least one silicon-based electronic integrated circuit disposed to
vertically stack with the SOI-based opto-electronic integrated circuit and
provide electrical control signals thereto; and

an optical input/output coupling element disposed over the SOI layer
of the vertically stacked arrangement to couple optical signals into and out
of the SOI-based opto-electronic integrated circuit.

4. The vertically stacked arrangement as defined in claim 1 wherein
the optical input/output coupling element comprises an inverse taper
coupling arrangement.

5. The vertically stacked arrangement as defined in claim 1 wherein
the optical input/output coupling element comprises a three-dimensional
adiabatically contoured coupling element to maintain the mode of the
propagating optical signal into and out of the SOI-based opto-electronic
integrated circuit.
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The Examiner relies on the following prior art references to show
unpatentability:
Delwala US 2002/0172464 A1 Nov. 21, 2002
Koh et al. US 2003/0113067 A1 Jun. 19, 2003

The Examiner maintains the following rejections:
1. Claims 1 and 4 rejected under 35 U.S.C. § 102(b) as anticipated by
Koh et al. (“Koh”); and
2. Claims 1 and 5 rejected under 35 U.S.C. § 102(b) as anticipated by
Delwala.
Since no claims are argued separately from the others, we decide this
Appeal on the basis of representative independent claim 1. See 37 C.F.R.
§ 41.37(c)(1)(vii) (“When multiple claims subject to the same ground of
rejection are argued as a group by appellant, the Board may select a single
claim from the group of claims that are argued together to decide the appeal
with respect to the group of claims as to the ground of rejection on the basis
of the selected claim alone.”). However, we further consider the meaning of
claims 4 and 5 based on our interpretation of independent claim 1.
I. REJECTION BASED ON KOH
A. ISSUE ON APPEAL
Appellants contend that “waveguide (50)” as taught by Koh is part of
the “silicon-on-insulator (SOI)-based opto-electronic integrated circuit” and
thus cannot be the “optical input/output coupling element disposed over the
SOI layer.” (App. Br. 4-5). The Examiner contends that “[t]he waveguiding
layer (50) is the coupling element and is a separate layer over the SOI
structure [which consists of layers] (10, 20, 10, 20).” (Ans. 5).
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An issue on appeal arising from the contentions of Appellants and the
Examiner is: is “waveguide (50)” as taught by Koh a separate “optical
input/output coupling element disposed over the SOI layer” as recited in
claim 1?
B. FACTUAL FINDINGS
The following Findings of Fact (FF) are directed to the above
identified issue on appeal:
1. The Summary of Appellants’ Specification describes “utilizing
an optical input/output coupling element in intimate contact with the SOI-
based opto-electronic circuit.” (Spec. ¶ 7).
2. Within the broad terms of this statement, the Specification
further describes embodiments in which the optical I/O coupling element is
disposed “within” the SOI layer as well as other embodiments in which the
coupling element is disposed “over” the SOI layer of the SOI-based opto-
electronic circuit (Spec. ¶¶ 18-21, 25 and 26-27; Figs. 1-2 and 5-6).
3. Appellants’ Specification also states that “[i]n certain
embodiments of the present invention, optical I/O coupling element 22 is
formed as an integral part of SOI-based circuit 12 (i.e., features directly
formed in SOI layer 18). In other cases, optical I/O coupling element 22
may comprise a separate, discrete component (e.g., optical prism).” (Spec. ¶
18).
4. Figures 1 and 2 of Appellants’ Specification (see, for example,
Figure 1 provided below) shows a separate optical I/O coupling element 22
as a pair of prisms 42 and 44 “disposed over,” or on top of, the SOI layer 18.
(Spec. ¶¶ 20 and 21; Figures 1 and 2).
Figure 1 is reproduced below:
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Figure 1 depicts, in a cut away side view, an exemplary vertical stack of
CMOS-based electronics and SOI-based opto-electronics. (Spec. ¶ 10).
5. Appellants’ Specification also states that
a grating structure may be etched into SOI-based
circuit 12, where the grating pitch and period are
controlled to provide the optical coupling.
Alternatively, an inverse taper structure or a three-
dimensional adiabatic horn taper element may be
used to couple an optical signal from a fiber or
optical device/waveguide into SOI layer 18.
(Spec. ¶ 20).
6. Figures 5 and 6 (Figures 5 and 6 are provided below) illustrate
alternative optical I/O coupling elements in the form of optical gratings 120
and 150, respectively, which are described as being formed “within SOI
layer 18.” (Spec. ¶¶ 26 and 27).
Figures 5 and 6 are reproduced below:
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Figures 5 and 6 depict isometric views of two SOI-based opto-electronic
integrated circuits, one with an optical grating 120 (Fig. 5) and one with an
inverse taper optical coupler 150 (Fig. 6). (Spec. ¶¶ 13-15 and 26-27).
7. Appellants’ Specification states that “[o]ptical I/O coupling
element 22 may comprise, as discussed above, a prism coupling structure, a
grating coupling, inverse taper coupling arrangement, three-dimensional
adiabatic horn taper or any other suitable structure for coupling a
propagating optical signal into and out of SOI layer 18.” (Spec. ¶ 29).
8. Claim 1 as originally filed with Appellants’ Specification
recites “an optical input/output coupling element disposed in conjunction
with the SOI layer” rather than the requirement that the optical I/O coupling
element be disposed “over” the SOI layer as is found in amended claim 1,
which is before us at present. (Spec., claim 1).
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9. Koh teaches that waveguide 50 is formed in an SOI layer
between an under-cladding Si layer 40 and an upper cladding Si layer 40,
which constitutes the silicon layer of the SOI layer. (Koh, ¶¶ 39 and 41-43;
Figures 5B-5D).
10. Otherwise, Koh teaches that the “silicon mirrors 36,
waveguide/silicon trenches 46, and MEMs acutators can provide optical I/O
coupling and optical switching functionalities.” (Koh, ¶ 31).
11. Koh demonstrates that silicon mirrors 36 are provided in
separate arrays from the SOI devices, which are manufactured separately
and are disposed adjacent one another. (Koh, ¶¶ 39-54; Figures 1A, 1B, 5A-
5F, 6A-6F).
12. Koh teaches that trenches 46 are formed from the space
between the array of mirrors 36 and the SOI device arrays. (Koh, ¶ 31;
Figure 1A).
C. PRINCIPLES OF LAW
Because claim interpretation normally controls the rest of the decision
making process, we start with an interpretation of the claims. Panduit Corp.
v. Dennison Mfg. Co., 810 F.2d 1561, 1567 (Fed. Cir. 1987)(“Analysis
begins with a key legal question -- what is the invention claimed?”). “[A]s
an initial matter, the PTO applies to the verbiage of the proposed claims the
broadest reasonable meaning of the words in their ordinary usage as they
would be understood by one of ordinary skill in the art, taking into account
whatever enlightenment by way of definitions or otherwise that may be
afforded by the written description contained in the applicant's
specification.” In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). “The
claims must be read in view of the specification, of which they are a part.
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The specification is always highly relevant. Usually, it is dispositive; it is the
single best guide to the meaning of a disputed term.” Phillips v. AWH
Corp., 415 F.3d 1303, 1315 (Fed. Cir. 2005).
“[R]ejections under 35 U.S.C. § 102 are proper only when the claimed
subject matter is identically disclosed or described ‘in the prior art.’” In re
Arkley, 455 F.2d 586, 587 (CCPA 1972). Therefore, in order to anticipate, a
reference must identify something falling within the claimed subject matter
with sufficient specificity to constitute a description thereof within the
purview of § 102. In re Schaumann, 572 F.2d 312, 317 (CCPA 1978).
D. ANALYSIS
We find that the term “over” as used in the phrase “an optical
input/output coupling element disposed over the SOI layer” is used by
Appellants in accordance with its ordinary and accustomed meaning of “on
top,” thereby limiting the claim to an optical I/O coupling element disposed
on top of the SOI layer. Morris, 127 F.3d at 1054. Appellants’
Specification clearly distinguishes between a first type of separate optical
I/O coupling element, for example prisms, disposed over an SOI layer, and a
second type of optical I/O coupling element, for example a grating, which is
formed directly within the SOI layer. (FF 3-6). Claim 1 as recited herein
clearly refers to the first type of I/O coupling element by requiring that the
optical I/O coupling element be disposed “over” or on top of the SOI layer.
(See claim 1). We particularly note that Appellants' amended claim 1 from
broader language that would have incorporated both types of optical I/O
coupling elements (also reflected in the Summary of the Invention in
Appellants’ Specification) to the present language which only reflects the
first type of optical I/O devices. (FF 1, 2 and 8; see also claim 1).
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Therefore, we determine that claim 1 requires the optical I/O coupling
element to be disposed on top of the SOI layer.
Koh does not teach such an arrangement. Rather, Koh teaches that
waveguide 50 is disposed within a SOI layer, similar to the second type of
optical I/O coupling element disclosed by Appellants, but not over the SOI
layer as required by claim 1. Likewise, the combination of waveguide 50,
trench 46 and silicon mirror 36, each of which contribute to optical
input/output are at best disposed adjacent to the SOI layer, and not “over”
the SOI layer as required by claim 1. Thus, despite whether waveguide 50
functions as a separate optical I/O coupling element apart from the SOI-
based opto-electronic integrated circuit, it is not disposed such that claim 1
reads on waveguide 50 of Koh. Thus, Koh does not identically disclose the
invention of claim 1, and Koh does not anticipate the invention recited in
claim 1. Arkley, 455 F.2d at 587.
Therefore, we cannot sustain the Examiner’s rejection of claims 1 and
4 under 35 U.S.C. § 102(b) as anticipated by Koh.
II. REJECTION BASED ON DELWALA
A. ISSUE ON APPEAL
Appellants contend that Delwala teaches “the integration of optic and
electronic devices within the same SOI structure” that “‘share’ the same
silicon layer (SOI layer), dielectric layer, and the like” and not a separate
“(SOI)-based opto-electric integrated circuit” and “silicon-based electronic
integrated circuit disposed to vertically stack with the SOI-based opto-
electronic integrated circuit” as recited in claim 1. (App. Br. 5). The
Examiner contends that reference numeral 5101 (Figs. 43 and 44) is a
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silicon-based electronic integrated circuit “stacked on the silicon surface
layer (160).” (Ans. 5-6).
An issue on appeal arising from the contentions of Appellants and the
Examiner is: does Delwala teach an electronic integrated circuit separate
from the SOI-based integrated circuit?
B. FACTUAL FINDINGS
The following additional Findings of Fact are directed to the above
identified issues on appeal:
13. Delwala teaches the use of prisms or gratings as the light
coupling portion 5110 of a light coupler 112, in which the prisms or gratings
are disposed over an SOI layer of a SOI-based opto-electronic integrated
circuit. (Delwala ¶¶ 115, 236, 245-250, 260, 263; see e.g., Figures 7A, 43,
45-46, 52 and 54).
14. Delwala teaches electronic devices 5101 may be fabricated
simultaneously on a single SOI wafer 152. (Delwala, ¶ 95).
15. Delwala also includes a broader teaching in which a SOI-based
integrated circuit 103 is provided on a first flip chip portion 5904 and
electronic devices 5101 are provided on a second flip chip portion 5902,
which is vertically disposed over the first flip chip portion 5904. (Delwala,
¶¶ 76-79, 259-268; Figures 51-54). Thus, the electronic devices are
provided on a separate “chip” from the SOI-based opto-electronic integrated
circuit.
16. Figure 52 shows prisms 5110 as the light coupling portion
disposed over a SOI layer 160 and show a separate electronic integrated
circuit 5101 provided in a flip chip 5902 disposed vertically over the SOI-
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based integrated circuit 152 provided in a separate flip chip 5904. (Delwala,
¶¶ 76-79, 259-268; Figure 52).
C. PRINCIPLES OF LAW
The same Principles of Law discussed above in section I are equally
relevant to the present issue.
D. ANALYSIS
Delwala teaches optical I/O coupling elements disposed over the SOI
layer of a SOI-based opto-electronic device. (FF 13 and 16). While
Delwala discloses integrating electronic devices and SOI-based opto-
electronic devices on a single SOI wafer (FF 14), Delwala also discloses an
alternative embodiment which incorporates the electronic devices 5101 on a
separate flip chip portion 5902. (FF 15 and 16). In such an arrangement, the
electronic devices 5101 are provided on a separate chip 5902 from the SOI-
based optoelectronic circuit, which is vertically disposed or stacked over, the
chip 5904 containing the SOI-based opto-electronic circuit 103. (FF 15 and
16). Thus, Delwala teaches an electronic integrated circuit separate from the
SOI-based integrated circuit. Appellants have not adequately demonstrated
that the teachings of Delwala are limited as suggested, and thus, Delwala
anticipates claim 1.
Therefore, we sustain the Examiner’s rejection of claims 1 and 5
under 35 U.S.C. § 102(b) as anticipated by Delwala.
III. NEW GROUND OF REJECTION – 35 U.S.C. § 112
The following is a quotation of the first paragraph of 35 U.S.C. § 112:
The specification shall contain a written
description of the invention, and of the manner and
process of making and using it, in such full, clear,
concise, and exact terms as to enable any person
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skilled in the art to which it pertains, or with which
it is most nearly connected, to make and use the
same, and shall set forth the best mode
contemplated by the inventor of carrying out his
invention.
Claims 4 and 5 are rejected under 35 U.S.C. § 112, first paragraph, as
lacking written description support in Appellants’ Specification. “The test
for determining compliance with the written description requirement is
whether the disclosure of the application as originally filed reasonably
conveys to the artisan that the inventor had possession at that time of the
later claimed subject matter, rather than the presence or absence of literal
support in the specification for the claim language.” In re Kaslow, 707 F.2d
1366, 1375 (Fed. Cir. 1983).
As discussed above, we find Appellants’ Specification reflects two
types of optical I/O coupling elements: a first type of separate optical I/O
coupling element, for example prisms, disposed over an SOI layer, and a
second type of optical I/O coupling element, for example a grating, which is
formed directly within the SOI layer. (FF 3-6). We also determined that
claim 1 was limited to the first type of optical I/O coupling element disposed
over an SOI layer. Thus, an optical I/O coupling element disposed within an
SOI layer does not fall within the scope of claim 1.
Claim 4 is dependent on claim 1 and recites that “the optical
input/output coupling element comprises an inverse taper coupling
arrangement.” (See claim 4). Appellants’ Specification lacks written
description of an “inverse taper coupling arrangement” disposed over, or on
top of, the SOI layer as required by claim 4. Appellants’ example of an
inverse taper coupling element is provided in Figure 6 and in paragraph 27
of Appellants’ Specification, in which the inverse taper is part of an optical
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coupling element that is disposed within the SOI layer. (FF 6). Appellants’
Specification does not convey to one of ordinary skill in the art that
Appellants were in possession of an inverse taper coupling arrangement
“disposed over the SOI layer” as required by claim 4 by virtue of its
dependence on claim 1. Kaslow, 707 F.2d at 1375. As such, claim 4 lacks
written description support in Appellants’ Specification.
Likewise, claim 5 recites “the optical input/output coupling element
comprises a three-dimensional adiabatically contoured coupling element to
maintain the mode of the propagating optical signal into and out of the SOI-
based opto-electronic integrated circuit.” Appellants’ Specification lacks
written description of a “three-dimensional adiabatically contoured coupling
element” disposed over, or on top of, the SOI layer as required by claim 5.
Appellants’ example of an adiabatically contoured coupling element is
provided in Figure 5 and in paragraph 26 of Appellants’ Specification, in
which the adiabatically contoured coupling element is disposed within the
SOI layer. (FF 6). Appellants’ Specification does not convey to one of
ordinary skill in the art that Appellants were in possession of a three-
dimensional adiabatically contoured coupling element “disposed over the
SOI layer” as required by claim 5 by virtue of its dependence on claim 1.
Kaslow, 707 F.2d at 1375. As such, claim 5 is lacks written description
support in Appellants’ Specification.
IV. CONCLUSION
We do not sustain the Examiner’s rejection of claims 1 and 4 based
on Koh, we sustain the Examiner’s rejection of claims 1 and 5 based on
Delwala, and we enter a new ground of rejection of claims 4 and 5 under 35
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U.S.C. § 112, first paragraph as lacking written description, pursuant to our
authority under 37 C.F.R. § 41.50(b).
V. DECISION
We affirm the decision of the Examiner with respect to claims 1 and
5, we reverse the decision of the Examiner with respect to claim 4, and we
enter a new ground of rejection with respect to claims 4 and 5.
VI. PROCEDURAL MATTERS
This decision contains a new ground of rejection pursuant to
37 C.F.R. § 41.50(b). This regulation provides that “[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
review.”
37 C.F.R. § 41.50(b) also provides that the Appellants, WITHIN
TWO MOTNHS FROM THE DATE OF THE DECISION, must exercise
one of the following two options with respect to the new ground of rejection
to avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an
appropriate amendment of the claims so rejected or
new evidence relating to the claims so rejected, or
both, and have the matter reconsidered by the
examiner, in which event the proceeding will be
remanded to the examiner….
(2) Request rehearing. Request that the
proceeding be reheard under § 41.52 by the Board
upon the same record….
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRM
37 C.F.R § 41.50(b)

cam

WENDY W. KOBA, ESQ.
P O BOX 556
SPRINGTOWN PA 18081
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