Ex Parte Seto et al

Board of Patent Appeals and Interferences

Mar 27, 2012

11097903 (B.P.A.I. Mar. 27, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/097,903 04/01/2005 Hui-Yin Seto 04-1999 1496.00414 3652
22501 7590 03/27/2012
CHRISTOPHER P MAIORANA, PC
LSI Corporation
24840 HARPER
SUITE 100
ST CLAIR SHORES, MI 48080
EXAMINER
TSENG, CHENG YUAN
ART UNIT PAPER NUMBER
2184
MAIL DATE DELIVERY MODE
03/27/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte HUI-YIN SETO and CHENG-GANG KONG
____________

Appeal 2009-013329
Application 11/097,903
Technology Center 2100
____________

Before MARC S. HOFF, CARLA M. KRIVAK, and
DENISE M. POTHIER, Administrative Patent Judges.

POTHIER, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2009-013329
Application 11/097,903

2
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b). We
reverse.

Invention
Appellants’ invention relates to a memory architecture that maximizes
an access timing margin. See Spec. 2. Claim 1 is reproduced below with the
key disputed limitations emphasized:
1. An apparatus comprising:
a control circuit configured to present a plurality of pairs of signals
in response to (i) one or more input data signals operating at a first
clock speed, (ii) one or more input address signals operating at said
first clock speed, and (iii) an input clock signal operating at a second
clock speed, wherein (a) a first one or more of said plurality of pairs
of signals comprise internal data signals, (b) a second one or more of
said plurality of pairs of signals comprise internal address signals, (c)
a second signal in each of said plurality of pairs of signals comprises a
clock signal operating at said second clock speed, and (d) said internal
data signals and said internal address signals operate at said second
clock speed;
a buffer circuit configured to generate a buffered signal in response
to each of said plurality of pairs of signals, wherein each of said
buffered signals operates at said second clock speed; and
a memory circuit configured to read and write data at said second
clock speed in response to said buffered signals.

The Examiner relies on the following as evidence of unpatentability:
Ranjan US 6,005,412 Dec. 21, 1999
Dong US 2003/0196032 A1 Oct. 16, 2003

Jennifer Tran, Xilink® Synthesizable DDR SDRAM Controller, XAPP200
(v2.4) 1-16 (2002) (“Xilink”).
Appeal 2009-013329
Application 11/097,903

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THE REJECTIONS
1. Claims 1-9 and 11-20 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Dong and Xilink. Ans. 3-9.1
2. Claim 10 is rejected under 35 U.S.C. § 103(a) as unpatentable over
Dong, Xilink, and Ranjan. Ans. 9-10.

THE OBVIOUSNESS REJECTION OVER DONG AND XILINK
Among other things, Appellants argue that Dong’s reference clock
signals are derived from the memory controller and thus cannot be an input
clock signal that (a) is used by the control circuit to generate the plurality of
pairs of signals and (b) operates at a second clock speed. App. Br. 9-11.
Appellants also assert that: (1) Dong teaches the system clock operates at 1x
speed; (2) Dong is inconsistent with the internal address signal operating at
the second clock speed; and (3) Xilink (a) teaches the address signals are
generated at a fpga_clk or a first clock speed and (b) does not cure the
deficiencies of Dong. App. Br. 10-13; Reply Br. 5-6.

ISSUES
Under § 103, has the Examiner erred by finding that Dong and Xilink
collectively would have taught or suggested (1) an input clock signal
operating at a second clock speed and (2) the internal address signals operate
at the second clock speed?

1 Throughout this opinion, we refer to (1) the Appeal Brief filed March 10,
2009; (2) the Examiner’s Answer mailed May 5, 2009; and (3) the Reply
Brief filed June 29, 2009.
Appeal 2009-013329
Application 11/097,903

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ANALYSIS
Based on the record before us, we find error in the Examiner’s
rejection of independent claim 1, which calls, in pertinent part, for an input
clock signal and the internal address signals to operate at the second clock
speed. We agree with Appellants that Dong’s reference clock shown in
Figure 5 cannot be the recited “input clock signal” (see Ans. 4), because
claim 1 requires that the control circuit be configured to present pairs of
signals in response to the input clock signal. That is, the Examiner maps the
internal data signal (i.e., a first one of the pairs of signals) to the data signal
from PLLs/buffers 500 to latch 505 and the internal address signal (i.e., a
second one of the pairs of signals) to the address signal from PLLs/buffers
500 to latch 505. See id. Based on this mapping, the input clock signal must
be arranged such that this clock signal is inputted prior to the mapped pairs
of signals so that the pairs of signals are presented in response to the input
clock signal as required by claim 1.
The Examiner, however, points to Figures 4-5 in Dong that include a
system clock (see Ans. 4-5, 12), which can be an input clock signal (see
Dong ¶ 0033; Figs. 4-5). Despite Appellants’ assertion (App. Br. 10 n. 40),
Dong does not state at what speed the system clock signal operates. Instead,
Dong discusses and shows that the timing of the address, data, and control
signals are relative to the reference clock such that the signals are generated
one reference clock cycle after the differential memory clocks are generated.
See Dong ¶ 0046; Fig. 6. On the other hand, Xilink teaches dividing a clock
signal (u_clk) into two clock speeds (e.g., fpga_clk, fpga_clk2x) at Clk_dlls
or at the beginning of the controller circuit, ddr_ctrl. Xilink, Fig. 4. Thus,
Appeal 2009-013329
Application 11/097,903

5
Xilink suggests an input clock signal can be operated at a second clock
speed.
Nonetheless, the Examiner’s findings (Ans. 5-6, 13) related to Xilink
do not further teach or suggest that Xilink’s internal address signals can
operate at the second clock speed. That is, Xilink shows that a data signal
(e.g., u_data_i) may enter at a first clock speed (e.g., fpga_clk) and the
internal data signals (ddr_dqs, ddr_dq) may exit a controller (e.g., ddr_ctrl)
at a second clock speed (e.g., clk2x). Xilink 3-5, 7; Figs. 3, 4, 7; Table 1.
While Xilink similarly shows both clock speeds entering the Addr_latch (see
Fig. 4), the speed at which the internal address signals (ddr_ad, ddr_ba)
operate is not discussed in these passages. See id. Nor has the Examiner
relied upon or formulated the obviousness rejection based on what Figure 4
teaches or suggests. See Ans. 5-6, 11-13. Also, Xilink’s teaching of using a
second clock speed by itself does not adequately demonstrate that an
ordinary skilled artisan would have found it obvious to operate the internal
address signal at a second clock speed as recited.
In fact, as Appellants state (App. Br. 12; Reply Br. 5-6), Xilink
teaches that the address signals are generated by fpga_clk during a write
operation or operate at a first data rate to guarantee DDR hold time. See
Xilink 13. This teaches that the internal address signals operate at the first
clock speed (see id.) and does not suggest that using a second clock speed
would be “obvious to try” (see Ans. 13). Also, Xilink only discusses data
signals (see Xilink, Fig. 13 showing DQs) – not address signals – during the
read operation. The Examiner has not adequately explained how Xilink’s
teaching of the read operation of data signals at a second clock speed (see
Ans. 5 citing to Xilink’s Fig. 13) would have equally been recognized by an
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Application 11/097,903

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ordinary skilled artisan for internal address signals (see Ans. 5-6, 11-13) and
thus has not sufficiently established a prima facie case of obviousness.
For the foregoing reasons, Appellants have persuaded us of error in
the rejection of: (1) independent claim 1; (2) independent claims 12 and 13,
which recite commensurate limitations; and (3) dependent claims 2-9, 11,
and 14-20 for similar reasons.

THE REMAINING OBVIOUSNESS REJECTION
Claim 10 depends from independent claim 1. The Examiner finds that
Dong, Xilink, and Ranjan teach all the limitations in this claim. The
Examiner has not relied on Ranjan to cure the above-noted deficiencies of
claim 1. See Ans. 10. Thus, because we reverse the Examiner’s rejection of
independent claim 1, we likewise will not sustain the rejection of claim 10.

CONCLUSION
The Examiner did not err in rejecting claims 1-20 under § 103.

DECISION
The Examiner’s decision rejecting claims 1-20 is reversed.

REVERSED

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