Ex Parte Sethuraman et al

Board of Patent Appeals and Interferences

Aug 29, 2012

10530495 (B.P.A.I. Aug. 29, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte RAMANATHAN SETHURAMAN,
BALAKRISHNAN SRINIVASAN, CARLOS ANTONIO
ALBA PINTO, HARM JOHANNES ANTONIUS PETERS,
and RAFAEL PESET LLOPIS
____________________

Appeal 2010-003763
Application 10/530,495
Technology Center 2100
____________________

Before JAMESON LEE, THOMAS S. HAHN, and JUSTIN T. ARBES,
Administrative Patent Judges.

ARBES, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF CASE
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-12 and 14-17, the only claims pending in the application on appeal.
Claim 13 was cancelled. We have jurisdiction over the appeal pursuant to
35 U.S.C. § 6(b).1
We reverse.
The claims are directed to a data processing apparatus and methods of
programming and using a data processing apparatus. Claim 1 is exemplary:
1. A data processing apparatus, the apparatus comprising:
an instruction address generation circuit for outputting an
instruction address;
an instruction memory system arranged to output an
instruction word addressed by the instruction address, including
at least one type of memory selected to achieve a desired
instruction cycle time wherein longer instruction words are
stored in said memory system within memory ranges of
progressively shorter instruction words associated with a
corresponding memory type;
an instruction execution unit, arranged to process a
plurality of instructions from the instruction work in parallel;
a detection unit, arranged to detect in which of a plurality
of ranges the instruction address lies, the detection unit being
coupled to the instruction execution unit parallelizes processing
of the instructions from the instruction word, dependent on a
detected range.2

1 Our decision will make reference to Appellants’ Amended Appeal Brief
(“App. Br.,” filed August 20, 2009) and Reply Brief (“Reply Br.,” filed
January 5, 2010), and the Examiner’s Answer (“Ans.,” mailed November 27,
2009) and Final Rejection (“Final Rej.,” mailed September 24, 2008).
2 We note that the claims submitted in the Claims Appendix of Appellants’
Appeal Brief are slightly different from those in effect at the time of the
Footnote continued on next page.
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REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Fisher
Jensen
US 6,026,479
US 7,149,878 B1
Feb. 15, 2000
Dec. 12, 2006
(filed Oct. 30, 2000)
Sanches
Maiyuran
US 2002/0116596 A1
US 2002/0129201 A1
Aug. 22, 2002
Sept. 12, 2002
Lilja David J. Lilja, “Exploiting the Parallelism
Available in Loops,” IEEE Computer, Vol. 27,
No. 2, Feb. 1994, pp. 13-26.

REJECTIONS
Claims 1-5, 7, and 15-17 were rejected under 35 U.S.C. § 103(a) as
being unpatentable over Fisher in view of Jensen. Ans. 3-8.
Claims 6 and 14 were rejected under 35 U.S.C. § 103(a) as being
unpatentable over Fisher in view of Jensen and Lilja. Ans. 8-9.
Claims 8 and 9 were rejected under 35 U.S.C. § 103(a) as being
unpatentable over Fisher in view of Jensen and Maiyuran. Ans. 9-11.

Final Rejection. See App. Br. 13-17; Amendment dated July 9, 2008, at 2-6.
For example, claim 1 in the Claims Appendix recites “at least one type of
memory suitable for a achieving a desired instruction cycle time wherein
longer instruction words are contained within ranges,” whereas the claim
rejected in the Final Rejection recited “at least one type of memory selected
to achieve a desired instruction cycle time wherein longer instruction words
are stored in said memory system within memory ranges.” Because no
amendment appears in the record following the Final Rejection, we use the
claims in effect at the time of the Final Rejection for purposes of this appeal.
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Claims 10 and 12 were rejected under 35 U.S.C. § 103(a) as being
unpatentable over Fisher in view of Jensen and Sanches. Ans. 11-13.
Claim 11 was rejected under 35 U.S.C. § 103(a) as being unpatentable
over Fisher in view of Jensen, Sanches, and Maiyuran. Ans. 13.

ANALYSIS
I. Obviousness Rejection of Claims 1-5, 7, and 15-17 (Fisher/Jensen)
Appellants argue that Fisher and Jensen do not suggest an instruction
memory system arranged to output an instruction word addressed by an
instruction address “wherein longer instruction words are stored in said
memory system within memory ranges of progressively shorter instruction
words associated with a corresponding memory type” as recited in claim 1.
App. Br. 7-8; Reply Br. 4-6. Specifically, Appellants read claim 1 to require
that instruction words be stored in memory in a particular order, i.e., in
ranges of “progressively shorter” instruction words where each range
corresponds with a particular memory type. App. Br. 8; Reply Br. 5-6.
According to Appellants, Fisher and Jensen do not suggest this “specific
ordering of the instructions based on word length.” Reply Br. 5.
The Examiner reads the disputed language of claim 1 differently,
however. In reading the claim language onto the disclosure of Fisher, the
Examiner finds that “the high [instruction level parallelism (ILP)]
instructions (i.e. longer instruction words) of Fisher must be stored within a
memory range that also stores low ILP instructions (i.e. shorter instruction
words) of the memory system.” Ans. 14 (emphasis added). Thus, the
Examiner appears to read the claim terms “longer” and “shorter” in relation
to each other such that the claim simply requires an instruction word of one
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width in a memory range that also includes an instruction word of smaller
width, without any particular ordering of ranges. Based on this reading of
the claim, the Examiner finds “a number of ways” in which Fisher inherently
discloses the limitation. Ans. 14. For example, “[i]f the memory range is
inclusive of the entire hard drive or disk, which is part of the memory
system, then Fisher inherently stores both high and low ILP instructions
within that range on the disk.” Ans. 14. The Examiner also points to Jensen
as teaching different types of instructions stored in the same single memory
range. Ans. 15.
Consequently, the issue before us is how the language of claim 1
should be interpreted when given its broadest reasonable interpretation in
light of the Specification. Appellants read the claim as requiring instruction
words stored in memory in a particular order, i.e., within a plurality of
memory “ranges” having instruction words of “progressively shorter” width
(App. Br. 7-8; Reply Br. 4-6), whereas the Examiner appears to read the
claim as requiring one memory “range” storing both “longer” and “shorter”
instruction words at the same time (Ans. 14-15). Based on the record before
us, we conclude that Appellants’ interpretation is the broadest reasonable
interpretation of the claim in light of the Specification and that the
Examiner’s interpretation is not reasonable.
We begin with the Specification, as it is the “single best guide to the
meaning of” claim language. Phillips v. AWH Corp., 415 F.3d 1303, 1315
(Fed. Cir. 2005) (citations and quotation marks omitted). Appellants’
Specification describes “a data processing apparatus, such as a VLIW (Very
Long Instruction Word) processor, that is capable of executing a plurality of
instructions from an instruction word in parallel.” Spec., pg. 1, ll. 1-3. As
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shown in Figure 2, exemplary instruction memory system 12 has two
memories 20 and 22, “each having locations that are addressed by [an]
instruction address, the locations having different width, dependent on the
memory.” Spec., pg. 6, ll. 27-28, Fig. 2. The instruction words in memory
20, used for the inner loop of a computer program, are wider than those of
memory 22. Spec., pg. 5, l. 30-pg. 6, 1. 7. According to Appellants, this
arrangement allows for “more efficient use of memory space” and increases
the efficiency of execution in the inner loop. Spec., pg. 6, ll. 5-7.
The Specification therefore contemplates one memory 20 storing very
long instruction words having a first width (e.g., 2 bytes) in a first range of
instruction addresses (e.g., address 0 to address 100), and another memory
22 storing very long instruction words having a second, smaller width (e.g.,
1 byte) in a second range of instruction addresses (e.g., address 101 to
address 300). This corresponds directly to the language of claim 1, which
recites longer instruction words stored within memory ranges of
“progressively shorter instruction words associated with a corresponding
memory type.” In addition, while the disclosed embodiment uses just two
memories, the Specification recognizes that “a greater number of such
memories could be used, each with its own width and each for its own range
of addresses.” Spec., pg. 6, ll. 28-30.
Appellants’ reading of the claim as requiring a particular ordering of
plural ranges also comports with the remainder of claim 1 and the language
of the dependent claims. See Phillips, 415 F.3d at 1314 (“the context in
which a term is used in the asserted claim can be highly instructive”). Claim
1 recites a detection unit that detects in which of a “plurality of ranges” (e.g.,
address 0 to address 100, address 101 to 300) a particular instruction address
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lies. Also, dependent claim 5 recites first and second memory units storing
instruction words of different lengths in first and second memory ranges,
respectively, and dependent claim 10 recites a plurality of memory units
“each arranged to be responsive to instruction addresses in a respective
range” that permits “partial overlap.” By contrast, the Examiner’s
interpretation of the claim essentially reads out the requirement of a plurality
of ranges. See, e.g., Ans. 14-15 (“the claimed limitation of storing longer
instruction words . . . within a memory range of shorter instruction words”)
(emphasis added). We interpret claim 1 to require a plurality of memory
ranges storing instruction words of “progressively shorter” width where each
range has a corresponding memory type.
In light of this interpretation, we disagree with the Examiner’s finding
that Fisher inherently teaches the claimed feature that “longer instruction
words are stored in said memory system within memory ranges of
progressively shorter instruction words associated with a corresponding
memory type.” See Ans. 14-15. Even assuming (without deciding) that
Fisher stores instruction words of multiple widths in a single range of
memory (e.g., an “entire hard drive or disk”) as the Examiner proposes, it
does not automatically follow that the memory would store instruction
words in the recited order – in ranges of “progressively shorter” instruction
words where each range corresponds with a particular memory type. See
Ans. 14; In re Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999) (“[Inherency
requires] that the missing descriptive matter is necessarily present in the
thing described in the reference, and that it would be so recognized by
persons of ordinary skill. . . . The mere fact that a certain thing may result
from a given set of circumstances is not sufficient.”) (citations and quotation
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marks omitted; emphasis added). Likewise, to the extent the Examiner relies
on Jensen as inherently teaching the claimed ordering (Ans. 15), we disagree
in light of the interpretation above.
We therefore are persuaded that the Examiner erred in finding that
Fisher and Jensen suggest an instruction memory system with the claimed
ordering of “progressively shorter” instruction words. Further, the Examiner
has not provided any basis or reason why the limitation would be obvious
based on the other cited references (Lilja, Maiyuran, or Sanches). See Ans.
8-13. Accordingly, we do not sustain the Examiner’s rejection of
independent claim 1, independent claim 15, which recites a commensurate
limitation, and dependent claims 2-5, 7, 16, and 17. Further, because we
find the above issue dispositive of the appeal, we need not reach the other
arguments raised by Appellants. See App. Br. 9-10.

II. Obviousness Rejections of Claims 6, 8-12, and 14
For the reasons discussed above, we agree with Appellants that Fisher
and Jensen do not suggest an instruction memory system arranged to output
an instruction word addressed by an instruction address “wherein longer
instruction words are stored in said memory system within memory ranges
of progressively shorter instruction words associated with a corresponding
memory type” as recited in claim 1. Claims 6 and 8-12 depend from claim
1, and independent claim 14 recites a commensurate limitation. We agree
with Appellants for the same reasons discussed above. Accordingly, based
on the record before us, we do not sustain the obviousness rejections of
dependent claims 6, 8-12, and 14.

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CONCLUSION
Appellants have persuaded us of error in the Examiner’s decision to
reject claims 1-12 and 14-17 under 35 U.S.C. § 103(a).

DECISION
For the above reasons, the rejections of claims 1-12 and 14-17 under
35 U.S.C. § 103(a) are reversed.

REVERSED

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