Ex Parte Schrieffer et al

Patent Trial and Appeal Board

Oct 30, 2018

13813767 (P.T.A.B. Oct. 30, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/813,767 02/01/2013
80711 7590 10/30/2018
BGL/ Ann Arbor
524 South Main Street
Suite 200
Ann Arbor, MI 48104
UNITED ST A TES OF AMERICA
FIRST NAMED INVENTOR
Jorn Schrieffer
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
14423-074 1792
EXAMINER
CHOI, CHARLES J
ART UNIT PAPER NUMBER
2133
MAIL DATE DELIVERY MODE
10/30/2018 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JORN SCHRIEFFER,
JURGEN SCHERSCHMIDT, and THOMAS PIECHL
Appeal2018-002383
Application 13/813, 7 67
Technology Center 2100
Before CARLA M. KRIVAK, JASON V. MORGAN, and
JEREMY J. CURCURI, Administrative Patent Judges.
KRIVAK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-9 and 11-15. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Appeal2018-002383
Application 13/813,767
STATEMENT OF THE CASE
Appellants' invention is directed to "an electronic memory
arrangement and to the use of the memory arrangement in motor vehicles"
(Spec. ,r 2).
Independent claim 1, reproduced below, is exemplary of the subject
matter on appeal.
1. An electronic memory arrangement comprising:
at least three memory areas;
a memory control unit;
a writing memory-accessing unit which is configured to
carry out a write access;
a reading memory-accessing unit which is configured to
carry out a read access;
wherein the memory control unit determines the write or
read access to the at least three memory areas;
wherein the memory control unit is configured such that
after a writing of a first data packet to one of the at least three
memory areas, a following second data packet to be written is
written to one of the at least three memory areas to which the
read access does not take place simultaneously during the write
access of the second data packet; and
the memory arrangement is configured to provide a
selecting-reading sample mode, wherein after a transmission of
a data freeze signal by the reading memory-accessing unit to the
memory control unit, data are preserved in one of the at least
three memory areas in an unchanged form for a defined period
of time until data are actually read out, whereupon a further
write access to a memory area last written to, wherein the
further write access must be concluded, is prevented or blocked
by the memory control unit until data have been read out of a
memory area at a later time or until a new data freeze signal is
sent by the reading memory-accessing unit.
2
Appeal2018-002383
Application 13/813,767
REJECTIONS and REFERENCES 1
The Examiner rejected claims 1-7, 9, and 11 under 35 U.S.C. § I03(a)
based upon the teachings of Byrne (US 2007/0180297 Al; Aug. 2, 2007),
Jackson (US 8,112,784 Bl; Feb. 7, 2012) and Fujimori (US 2007/0091498
Al; Apr. 26, 2007).
The Examiner rejected claim 8 under 35 U.S.C. § I03(a) based upon
the teachings of Byrne, Jackson, Fujimori, and Matsunami (US 5,802,345;
Sept. 1, 1998).
The Examiner rejected claim 12 under 35 U.S.C. § I03(a) based upon
the teachings of Byrne, Jackson, Fujimori, and Conte (US 2010/0299481
Al; Nov. 25, 2010).
The Examiner rejected claims 13 and 14 under 35 U.S.C. § I03(a)
based upon the teachings of Byrne, Jackson, Fujimori, and Dickinson (US
2002/0069321 Al; June 6, 2002).
The Examiner rejected claim 15 under 35 U.S.C. § I03(a) based upon
the teachings of Byrne, Jackson, Fujimori, and Stence (US 2004/0044849
Al; Mar. 4, 2004).
ANALYSIS
Appellants contend the Examiner errs in finding Byrne does not
explicitly teach the claim limitation "the read access does not take place
simultaneously during the write access of the second data packet" ( emphasis
1 The Examiner claims rejected claimsl-15 under 35 U.S.C. § 112, second
paragraph (Final Act. 2). This rejection was withdrawn after Appellants
corrected an antecedent basis problem in claim 1 (Advisory Act. Mailed
Sept. 27, 2016).
3
Appeal2018-002383
Application 13/813,767
omitted), but finds Jackson teaches this limitation (Final Act. 4, citing
Jackson col. 11, 11. 41--43). Specifically, Appellants contend, "Jackson only
teaches that hard drives exist which cannot store and retrieve data
simultaneously," therefore the storage device in Jackson is equivalent to an
electronic memory arrangement (Br. 10). As such, Jackson does not disclose
a memory capable of simultaneously storing and retrieving data, where, in
one memory area, writing and reading does not occur at the same time (id.).
"Even in combination with Byrne the person skilled in the art would not
arrive at the present invention as neither Byrne nor Jackson give any hint
how to combine multiple memory areas such that simultaneous write and
read access to this electronic memory arrangement is possible while
preventing a simultaneous write access and read access to a specific memory
area" (id.). We agree.
The Examiner has cited Jackson stating "Jackson in col. 11, lines 41-
43 shows examples of storage devices 408 as being hard drives which
cannot both store and retrieve (i.e. write and read) data simultaneously"
(Ans. 9-10). The Examiner, however, has not specifically identified how
Jackson, in combination with Byrne and Fujimori, teaches or suggests
multiple memory areas where simultaneous write and read access to the
various memory areas is possible while preventing a simultaneous read
access to a specific area.
Thus, for these reasons we do not sustain the Examiner's rejection of
claim 1 dependent claims 2-9 and 11-15 argued therewith.
4
Appeal2018-002383
Application 13/813,767
DECISION
The Examiner's decision rejecting claims 1-9 and 11-15 is reversed.
REVERSED
5