Ex parte SCEPANOVIC et al.

Board of Patent Appeals and Interferences

May 7, 1998

08229624 (B.P.A.I. May. 7, 1998)

Application for patent filed April 19, 1994.1
1
THIS OPINION WAS NOT WRITTEN FOR PUBLICATION
The opinion in support of the decision being entered today (1)
was not written for publication in a law journal and (2) is
not binding precedent of the Board.
Paper No. 15
UNITED STATES PATENT AND TRADEMARK OFFICE
__________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
__________
Ex parte RANKO SCEPANOVIC,
JAMES S. KOFORD,
EDWIN E. JONES,
DOUGLAS B. BOYLE, and
MICHAEL D. ROSTOKER
__________
Appeal No. 97-2053
Application 08/229,6241
__________
ON BRIEF
__________
Before KRASS, JERRY SMITH, and FLEMING, Administrative Patent
Judges.
JERRY SMITH, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on the appeal under 35 U.S.C. § 134
from the examiner's rejection of claims 1-27, which constitute
all the claims in the application. In the answer the examiner
withdrew the pending rejection of claims 1-27 and added a
Appeal No. 97-2053
Application 08/229,624
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single new ground of rejection of claims 1, 15 and 17. Claims
2-14, 16 and 18-27 were indicated as now containing
allowable subject matter. Accordingly, this appeal is now
directed to the rejection of claims 1, 15 and 17.
The disclosed invention pertains to a computing method
and apparatus for computing a cost factor associated with the
placement of cells on an integrated circuit chip.
Representative claim 1 is reproduced as follows:
1. A computing apparatus for computing a cost factor of
a placement of cells on an integrated circuit chip and
interconnect nets for said placement, comprising:
a bounder for constructing bounding boxes around said
interconnect nets respectively; and
a processor for computing overlap of said bounding boxes
and computing said cost factor as a first predetermined
function of said overlap.
The examiner cites the following references:
Antreich et al. (Antreich) 5,267,176 Nov. 30, 1993
Kim 5,398,195 Mar. 14, 1995
(filed Feb. 21, 1992)
Noble 5,392,222 Feb. 21, 1995
(filed Dec. 30, 1991)

Appeal No. 97-2053
Application 08/229,624
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Claims 1, 15 and 17 stand rejected under 35 U.S.C. §
103. As evidence of obviousness the examiner offers Noble
taken alone.
Rather than repeat the arguments of appellants or the
examiner, we make reference to the briefs and the answers for
the respective details thereof.
OPINION
We have carefully considered the subject matter on
appeal, the rejection advanced by the examiner and the
evidence of obviousness relied upon by the examiner as support
for the rejection. We have, likewise, reviewed and taken into
consideration, in reaching our decision, the appellants'
arguments set forth in the briefs along with the examiner's
rationale in support of the rejection and arguments in
rebuttal set forth in the examiner's answers.
It is our view, after consideration of the record
before us, that the evidence relied upon and the level of
skill in the particular art would not have suggested to one of
Appeal No. 97-2053
Application 08/229,624
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ordinary skill in the art the obviousness of the invention as
set forth in claims 1, 15 and 17. Accordingly, we reverse.
In rejecting claims under 35 U.S.C. § 103, it is
incumbent upon the examiner to establish a factual basis to
support the legal conclusion of obviousness. See In re Fine,
837 F.2d 1071, 1073, 5 USPQ2d 1596, 1598 (Fed. Cir. 1988).
In so doing, the examiner is expected to make the factual
determinations set forth in Graham v. John Deere Co., 383 U.S.
1, 17, 148 USPQ 459, 467 (1966), and to provide a reason why
one having ordinary skill in the pertinent art would have been
led to modify the prior art or to combine prior art references
to arrive at the claimed invention. Such reason must stem
from some teaching, suggestion or implication in the prior art
as a whole or knowledge generally available to one having
ordinary skill in the art. Uniroyal Inc. v. Rudkin-Wiley
Corp., 837 F.2d 1044, 1051, 5 USPQ2d 1434, 1438 (Fed. Cir.),
cert. denied, 488 U.S. 825 (1988); Ashland Oil, Inc. v. Delta
Resins & Refractories, Inc., 776 F.2d 281, 293, 227 USPQ 657,
664 (Fed. Cir. 1985), cert. denied, 475 U.S. 1017 (1986); ACS
Hospital Systems, Inc. v. Montefiore Hospital, 732 F.2d 1572,
Appeal No. 97-2053
Application 08/229,624
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1577, 221 USPQ 929, 933 (Fed. Cir. 1984). These showings by
the examiner are an essential part of complying with the
burden of presenting a prima facie case of obviousness. Note
In re Oetiker, 977 F.2d 1443, 1445, 24 USPQ2d 1443, 1444 (Fed.
Cir. 1992).
According to the examiner, Noble teaches a means for
constructing bounding boxes around the interconnect nets of
the integrated circuit and a means for computing the amount of
overlap of the bounding boxes [answer, pages 3-4]. The
examiner concludes that based on this disclosure, it would
have been obvious to the artisan to compute the cost factor as
a predetermined function of bounding box overlap because it
would enhance the field of view [Id.].
Appellants argue that Noble fails to teach or suggest
the following features set forth in each of independent claims
1, 15 and 17:
(1) performing a placement of cells on
an integrated circuit chip;
(2) computing a cost factor or
congestion for the placement of cells
on an integrated circuit chip;
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Application 08/229,624
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(3) constructing bounding boxes around
the interconnect nets for the cell
placement; and
(4) computing the cost factor for the
cell placement as a first
predetermined function of the bounding
box overlap;
[see reply brief, pages 4-6].
The examiner responds that the claims do not require
placing cells on the integrated circuit [supplemental answer,
page 1]. The examiner notes that “[t]he claims require
computing overlap of said bounding boxes and the cost factor
as a function of the overlap (see claims 1, 15 and 17), but
not cost factor for the placement of cells on an integrated
circuit (IC) chip as cited” [ Id., page 3]. Finally, the
examiner reinforces this position by stating that “[t]he
rejected claims 1, 15 and 17 do not require locating cells on
a surface of an IC chip” [Id.].
In our view, the examiner has not properly considered
all of the claim recitations. Although we can agree that
Noble does broadly construct bounding boxes around
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Application 08/229,624
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interconnect nets, and Noble does broadly compute an overlap
of these bounding boxes, we cannot agree that Noble suggests
the computation of the cost factor as set forth in the claims
on appeal. Any cost factor in Noble is related to the best
location of a field of view for accessing a specific portion
of an integrated circuit. Noble has absolutely nothing to do
with determining the placement of cells on an integrated
circuit chip. Noble deals with an integrated circuit which
has already been designed and manufactured.
Claims 1 and 17 recite the function of “computing said
cost factor as a first predetermined function of said
overlap.” The phrase “said cost factor” refers to a cost
factor defined in the preamble of each of these claims.
Specifically, each of claims 1 and 17 defines the cost factor
in terms of “a placement of cells” on an IC chip or on a
surface. Therefore, the computation of this cost factor must
also be related to such cell placement. As noted above, Noble
has nothing to do with computing cost factors which relate to
such cell placement. Thus, the artisan would not have found
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Application 08/229,624
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it obvious to compute cost factors related to cell placement
in view of the teachings of Noble.
Claim 15 is similar to claims 1 and 17 except that the
cost factor is recited as a “congestion” in the placement of
cells on an integrated circuit chip and the claim recites
“computing said congestion.” For the same reasons discussed
above, the computation of claim 15 must be in relation to a
placement of cells on an integrated circuit chip. Since Noble
has nothing to do with such placement, the invention of claim
15 would not have been obvious in view of the teachings of
Noble.
In summary, the examiner’s position that the claims on
appeal do not require the placement of cells on an integrated
circuit chip is in error. The definition of cost factor or
congestion in the appealed claims requires that the cost
factor or congestion be related to the placement of cells on
an integrated circuit chip. For reasons discussed above,
Noble does not teach or suggest such a computation of cost or
congestion. Therefore, we do not sustain the rejection of
claims 1, 15 and 17 based on the teachings of Noble.
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Application 08/229,624
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In conclusion, the decision of the examiner rejecting
claims 1, 15 and 17 is reversed.
REVERSED
Errol A. Krass )
Administrative Patent Judge )
)
)
) BOARD OF PATENT
Jerry Smith ) APPEALS AND
Administrative Patent Judge ) INTERFERENCES
)
)
)
Michael R. Fleming )
Administrative Patent Judge )
Poms, Smith, Lande & Rose
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