Ex Parte Sato et alDownload PDFBoard of Patent Appeals and InterferencesAug 21, 201209771547 (B.P.A.I. Aug. 21, 2012) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 09/771,547 01/30/2001 Toshiyuki Sato D-1059 8819 7590 08/21/2012 HAUPTMAN KANESAKA BERNER PATNET AGENTS, LLP 1700 Diagonal Road Suite 310 Alexandria, VA 22314 EXAMINER AGGARWAL, YOGESH K ART UNIT PAPER NUMBER 2622 MAIL DATE DELIVERY MODE 08/21/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte TOSHIYUKI SATO and SATOSHI TOKUDA ____________ Appeal 2010-005112 Application 09/771,547 Technology Center 2600 ____________ Before DEBRA K. STEPHENS, DAVID M. KOHUT and RAMA G. ELLURU, Administrative Patent Judges. ELLURU, Administrative Patent Judge. DECISION ON APPEAL Appeal 2010-005112 Application 09/771,547 2 I. STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134(a) from the Examiner‟s non- final rejection of claims 1, 4, 5, and 7. (App. Br. 2). We have jurisdiction under 35 U.S.C. § 6(b). We affirm. Appellants’ Invention Appellants‟ inventions “relates to a radiation detector for industrial and medical purposes, more particularly, a direct-converting-type radiation detector using a converting layer for absorbing light or radiation to generate a pair of electron-hole[s].” (Spec. ¶ [0001]). Illustrative Claim 1. A radiation detector comprising: an active matrix board including gate lines and data lines arranged in a two-dimensional lattice shape, a plurality of high- speed switching elements provided at respective lattice points and connected to the gate lines and the data lines, each switching element being formed of a polycrystalline silicon thin film transistor and having a source electrode, pixel electrodes connected to the source electrodes of the high-speed switching elements, and charge storage capacitances, each being disposed between the pixel electrode and a ground electrode; and a converting layer, formed on the pixel electrodes, to generate a pair of electron-holes by absorbing radiation, said converting layer being formed of a vapor-deposited polycrystalline film of CdTe or CdZnTe. Prior Art Relied Upon Ikeda US 6,403,965 B1 Jun. 11, 2002 Yamazaki US 2002/0163035 A1 Nov. 7, 2002 Appellants‟ Admitted Prior Art (AAPA) Appeal 2010-005112 Application 09/771,547 3 Rejections on Appeal 1. Claims 1, 4, and 7 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Appellants‟ “admitted prior art” in view of Ikeda. (Ans. 4-5). 2. Claim 5 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Appellants‟ “admitted prior art” in view of Ikeda and Yamazaki. (Ans. 6-7). Examiner’s Findings and Conclusions 1. The Examiner finds that Ikeda teaches the motivation to combine the teachings of Appellants‟ admitted prior art with Ikeda to use poly-silicon as the TFT forming material in order to decrease the size of a TFT so that the effective area of each pixel can be increased. (Ans. 6 (citing Ikeda 12:1-10)). In addition, because the peripheral circuits can be prepared on the same glass substrate, it allows for a decrease in production costs, including the costs for the peripheral circuits. (Id.) 2. The Examiner recognizes the incompatibility taught in Appellants‟ admitted prior art—if a polycrystalline film of CdTe and CdZnTe is formed as a converting layer, instead of amorphous selenium, a film forming temperature higher than 300 degrees C° is required, but the active matrix board made of TFT (thin-film transistor) amorphous silicon, poses a problem because of the limited heat resistant temperature of 250 degrees C°. (Ans. 7). Thus, as the Examiner recognizes, the heart of Appellants‟ invention is to form the switching elements from poly- crystalline silicon TFT having a film-forming temperature of more than 300 degrees C° to combat the problem recognized in Appellants‟ admitted prior Appeal 2010-005112 Application 09/771,547 4 art. (Id.) The Examiner further recognizes that Ikeda teaches that the purpose of using polysilicon to form the TFTs (i.e., the claimed “switching elements”) is to decrease the size of a TFT so that the effective area of each pixel can be increased. (Ans. 8 (citing Ikeda (Figures 1 and 2)). The Examiner concludes, however, that while there must be motivation to make the claimed invention, there is no requirement that the prior art provide the same advantage or result as discovered by the Applicants to make the claimed invention. (Ans. 10 (citing MPEP § 2144 and In re Linter, 458 F.2d 1013 (CCPA 1972)). Appellants’ Contentions Appellants contend that: 1. There is no suggestion or motivation in either Appellants‟ “admitted prior art” or Ikeda that would lead a person of ordinary skill in the art to select the references and combine them in a way that would result in the invention claimed by any of claims 1, 4, and 7 (App. Br. 7-8); 2. The Examiner used impermissible hindsight to arrive at the proposed modification (App. Br. 11); 3. Ikeda does not teach or suggest the claim element “each switching element being formed of a polycrystalline silicon thin film transistor” as recited because the purpose of using polysilicon to form the thin film resistor (“TFT”) is to reduce the size of the TFT so that the effective area of each pixel can be increased. (App. Br. 9-10). According to Appellants, the claimed invention is based on part in developing a solution to the problem that there is an incompatibility between the film forming temperature required for a polycrystalline film of CdTe and CdZnTe as a Appeal 2010-005112 Application 09/771,547 5 converting layer and the heat resistant temperature of TFTs formed from amorphous silicon. (Reply Br. 5; See Ans. 7 (citing Appellants‟ “admitted prior art” ¶ 10)). Thus, Appellants conclude, the problem disclosed in Appellants‟ admitted prior art deters a person of ordinary skill from directly forming a polycrystalline film of CdTe and CdZnTe on the active matrix board formed from amorphous silicon, and does not lead a person of ordinary skill to use poly-silicon as the material for TFTs. (Reply Br. 5-6). II. ISSUES 1. Did the Examiner err in concluding that the combination of Appellants‟ “admitted prior art” and Ikeda renders claims 1 unpatentable because the recited limitations are not taught or suggested? 2. Did the Examiner improperly combine AAPA and Ikeda? III. ANALYSIS We have reviewed the Examiner‟s rejection in light of Appellants‟ contention that the Examiner has erred. We disagree with Appellants‟ conclusions and instead agree with and adopt the Examiner‟s findings and conclusions. We highlight and address specific arguments for emphasis as follows. Claims 1, 4, and 7: 35 U.S.C. § 103(a) Rejection—Combination of Appellants’ “admitted prior art” and Ikeda We find that the Examiner has identified a reasonable motivation to combine the “admitted prior art” and Ikeda. Specifically, Ikeda teaches using poly-silicon as the material for TFTs in order to decrease the size of a TFT so that the effective area of each pixel can be increased. (Ans. 6). Appeal 2010-005112 Application 09/771,547 6 Also, the Examiner explains that because the peripheral circuits can be prepared on the same glass substrate, it is possible to decrease production costs including the costs for the peripheral circuits. (Id. (citing Ikeda 12:1- 10)). We are not persuaded that the Examiner improperly used hindsight to identify the motivation to combine. In addition, it is of no matter that Ikeda teaches using poly-silicon for the TFTs (the claimed “switching elements”) for a different purpose, i.e., to decrease the size of TFTs (Ans. 8), than recognized by Appellants, i.e., to increase the heat resistance of the active matrix board to withstand the film- forming temperature required for a stable polycrystalline converting layer, including CdTe and CdZnTe (Ans. 8 (citing Spec. ¶ [0029])). In In re Lintner, the court stated: The fact that appellant uses sugar for a different purpose does not alter the conclusion that its use in a prior art composition would be prima facie obvious from the purpose disclosed in the references. Differences between a patent applicant's and the prior art‟s motivation for adding an element to a composition may be reflected in the composition ultimately produced. A claimed composition may possess unexpectedly superior properties or advantages as compared to prior art compositions. In this way, the conclusion of prima facie obviousness may be rebutted and the claimed subject matter ultimately held to be legally nonobvious. In re Lintner, 458 F.2d at 1016 (emphasis added). See also 2 D. Chisum, Patents, § 5.04[6] at 5-325 (1989) (“The fact that the prior art „suggests' the modification for a different purpose is irrelevant to the issue of prima facie obviousness though it is relevant to rebuttal of prima facie obviousness.”). Therefore, we agree with the Examiner‟s findings that the combination of Appeal 2010-005112 Application 09/771,547 7 the “admitted prior art” and Ikeda teaches or suggests all the disputed limitations of claims 1, 4, and 7. Claim 5: 35 U.S.C. § 103(a) Rejection—Combination of Appellants’ “Admitted Prior Art,” Ikeda, and Yamazaki Appellants argue that Yamazaki‟s disclosure does not rectify the deficiencies of the “admitted prior art” and Ikeda as argued with respect to claims 1, 4, and 7. (App. Br. 11-12). For the same reasons discussed above with respect to claim 1, we agree with the Examiner‟s conclusion that the combination of Appellants‟ “admitted prior art,” Ikeda, and Yamazaki discloses all the disputed limitations of claim 5. IV. CONCLUSION The Examiner has not erred in rejecting claims 1, 4, 5, and 7 as being unpatentable under 35 U.S.C. § 103(a) for the reasons discussed above. Claims 1, 4, 5, and 7 are unpatentable. V. DECISION We affirm the Examiner‟s decision to reject claims 1, 4, 5, and 7. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED ELD Copy with citationCopy as parenthetical citation