Ex Parte Saia et al

Patent Trial and Appeal Board

Dec 31, 2018

14091622 (P.T.A.B. Dec. 31, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/091,622 11/27/2013
6147 7590 01/03/2019
GENERAL ELECTRIC COMPANY
GPO/GLOBAL RESEARCH
901 Main Avenue
3rd Floor
Norwalk, CT 06851
FIRST NAMED INVENTOR
Richard Joseph Saia
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
269161-1 9697
EXAMINER
CHANG,JAYC
ART UNIT PAPER NUMBER
2895
NOTIFICATION DATE DELIVERY MODE
01/03/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
haeckl@ge.com
gpo.mail@ge.com
Lori.e.rooney@ge.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RICHARD JOSEPH SAIA, STEPHEN DALEY ARTHUR,
ZACHARY MATTHEW STUM, ROGER RAYMOND KOVALEC, and
GREGORY KEITH DUDOFF
Appeal2018-001896
Application 14/091,622
Technology Center 2800
Before MICHAEL P. COLAIANNI, RAEL YNN P. GUEST, and
JEFFREY R. SNAY, Administrative Patent Judges.
SNAY, Administrative Patent Judge.
DECISION ON APPEAL 1
Appellant2 appeals under 35 U.S.C. § 134(a) from the Examiner's
decision rejecting claims 1, 3-11, and 13-20. We have jurisdiction under
35 U.S.C. § 6(b).
We affirm.
1 We cite the Specification ("Spec.") filed November 27, 2013; Final Office
Action ("Final Act.") dated January 25, 2017; Appellant's Appeal Brief
("Br.") dated June 19, 2017; and Examiner's Answer ("Ans.") dated October
3,2017.
2 Appellant is General Electric Company, which also is identified as the real
party in interest. Br. 3.
Appeal2018-001896
Application 14/091,622
BACKGROUND
The subject matter on appeal is directed to metal-oxide-semiconductor
(MOS) devices. Spec. ,r 1. According to the Inventors, MOS devices
having gate electrodes with vertical sidewalls may disadvantageously
increase the etching rate of a gate oxide layer positioned beneath the gate
electrode, leading to trenching in the gate oxide layer. Id. ,r 26. The
Specification describes a MOS device in which a gate electrode has a sloped
or tapered sidewall which, according to the Inventors, may reduce or
eliminate trenching in the gate oxide layer. Id. ,r 30. Claim 1 reads:
1. A silicon carbide (SiC) semiconductor device,
compnsmg:
a gate oxide layer disposed on top of a SiC
semiconductor layer; and
a gate electrode comprising a polysilicon layer having a
tapered sidewall comprising a substantially tapered edge and
disposed on top of the gate oxide layer and a metal silicide layer
having a substantially vertical edge and disposed on top of the
polysilicon layer, wherein a shape of the tapered sidewall
reduces trenching in the gate oxide layer near a plurality of
edges of the gate electrode with a controlled thickness of the
gate oxide layer,
wherein an angle of the substantially tapered edge
relative to a surface of the semiconductor device comprises an
angle between approximately 65 degrees and approximately 85
degrees and further wherein the angle of the substantially
tapered edge and the shape of the tapered sidewall result from a
first vertical and a first lateral etching rate of the metal silicide
layer relative to a second vertical and a second lateral etching
rate at the top of the polysilicon layer and a third lateral etching
rate at the bottom of the polysilicon layer, wherein the first
vertical etching rate exceeds the first lateral etching rate and
further wherein the third lateral etching rate is approximately 0
A/min.
2
Appeal2018-001896
Application 14/091,622
Br. 20 (Claims Appendix).
REJECTIONS
I. Claims 1, 4, 5, 10, 11, and 13-15 stand rejected under 35 U.S.C.
§ I03(a) as unpatentable over Yamada3 and Shingu. 4
II. Claim 3 stands rejected under 35 U.S.C. § I03(a) as unpatentable over
Yamada, Shingu, and Rama. 5
III. Claims 6 stands rejected under 35 U.S.C. § I03(a) as unpatentable
over Yamada, Shingu, and Itonaga. 6
IV. Claims 7-9 stand rejected under 35 U.S.C. § I03(a) as unpatentable
over Yamada, Shingu, Itonaga, and Wang. 7
V. Claims 16-20 stand rejected under 35 U.S.C. § I03(a) as unpatentable
over Yamada, Shingu, and Itonaga.
OPINION
Rejection I
Appellant does not separately argue any claim, and focuses the
arguments solely on features found in claim 1. We select claim 1 as
representative.
Relevant to Appellant's arguments on appeal, the Examiner, referring
to Figure 2F of Yamada, finds that Yamada discloses a semiconductor
device which includes a gate electrode 102, having a tapered sidewall,
3 US 2011/0284935 Al, published November 24, 2011 ("Yamada").
4 US 2008/0093676 Al, published April 24, 2008 ("Shingu").
5 US 2012/0032151 Al, published February 9, 2012 ("Rama").
6 US 2002/0061639 Al, published May 23, 2002 ("Itonaga").
7 US 6,350,684 Bl, issued February 26, 2002 ("Wang").
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Appeal2018-001896
Application 14/091,622
disposed on top of a gate insulating layer 101. Yamada's Figure 2F is
reproduced below:
FIG.2F
r-1 OSa
150-,p 30-"
L104
102 109b 114
'
111
110 -~4~Slt::::t::W~~~
~~-,,..,,..::,i 109a
---106
100
't 03 101
Figure 2F is a cross-sectional view of a semiconductor device.
Appellant acknowledges that Yamada discloses a tapered gate
electrode, but argues that Yamada fails to teach that the tapered shape
reduces trenching. Br. 11.
The Examiner responds that the reduction in trenching that Appellant
relies upon is attributable to the gate electrode's sloped sidewalls and, for
that reason, Appellant's argument does not structurally distinguish the
claimed device from that of Yamada. Ans. 4.
After careful consideration of the evidence presented by the
Examiner, in light of Appellant's countervailing arguments, we are not
persuaded of reversible error. The Specification explains that providing a
gate electrode with tapered sidewalls results in shallower trenches or the
elimination of trenches in the gate oxide layer. Spec. 30. Indeed, claim 1
recites that "a shape of the tapered sidewall reduces trenching in the gate
4
Appeal2018-001896
Application 14/091,622
oxide layer." Appellant does not point to any structure other than the above-
noted sloped sidewalls that is necessary to achieve the recited reduction in
trenching. As such, Appellant does not persuade us that Yamada's gate
electrode having sloped sidewalls would have lacked the claimed
functionality of reducing trenching.
Appellant also argues that Yamada fails to disclose that the tapered
sidewall results from the recited etching process. Br. 11. Particularly, claim
1 recites, "the angle of the substantially tapered edge and the shape of the
tapered sidewall result from a first vertical and a first lateral etching rate of
the metal silicide layer relative to a second vertical and a second lateral
etching rate at the top of the polysilicon layer and a third lateral etching rate
at the bottom of the polysilicon layer." This recitation refers to the manner
in which the gate electrode's sidewall is formed. However, Appellant does
not point to any structural feature attributable to the recited fabrication
process that would differ from the structure taught by Yamada. See In re
Thorpe, 777 F .2d 695, 697 (Fed. Cir. 1985) ("The patentability of a product
does not depend on its method of production. If the product in a product-by-
process claim is the same as or obvious from a product of the prior art, the
claim is unpatentable even though the prior product was made by a different
process." (citation omitted)).
Appellant further argues that Shingu does not overcome the asserted
deficiency in Yamada. Br. 12-18. Because we are not persuaded of any
deficiency with regard to the Examiner's reliance on Yamada, this argument
also is not persuasive.
For the foregoing reasons, Rejection I is sustained.
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Appeal2018-001896
Application 14/091,622
Rejections 11-V
Appellant does not argue any of Rejections II-V except for an implicit
reliance on the arguments presented against Rejection I. Accordingly, we
sustain Rejections II-V for the reasons set forth above in connection with
Rejection I.
DECISION
The Examiner's decision rejecting claims 1, 3-11, and 13-20 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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