Ex Parte Röhner et al

Patent Trial and Appeal Board

Sep 19, 2018

14151528 (P.T.A.B. Sep. 19, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/151,528 01/09/2014 Michael Rohner
57579 7590 09/21/2018
MURPHY, BILAK & HOMILLER/INFINEON TECHNOLOGIES
1255 Crescent Green
Suite 200
CARY, NC 27518
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1012-0748 / 2013P51770 1414
us
EXAMINER
RODRIGUEZ, DOUGLAS X
ART UNIT PAPER NUMBER
2858
NOTIFICATION DATE DELIVERY MODE
09/21/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
official@mbhiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL ROHNER, STEP ANO ARESU,
and MARCO FARICELLI
Appeal2017-008799
Application 14/151,528 1
Technology Center 2800
Before JEFFREY T. SMITH, BEYERL YA. FRANKLIN, and
JEFFREY R. SNAY, Administrative Patent Judges.
SMITH, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134, Appellant seeks our review of the
Examiner's rejections of claims 1-29. We have jurisdiction. 35 U.S.C. § 6.
We reverse.
STATEMENT OF THE CASE
According to the Specification, Appellant's invention relates to
assessing dielectric reliability of a semiconductor technology. (Spec. ,r 1.)
1 Appellant is the Applicant, INFINEON TECHNOLOGIES AG, which is
also identified as the real party in interest. (App. Br. 2.)
Appeal2017-008799
Application 14/151,528
Independent claim 1 is illustrative of the appealed subject matter, and
is reproduced below:
1. A semiconductor wafer, comprising:
dielectric regions of different thicknesses, some of the
dielectric regions being thinner and other ones of the dielectric
regions being thicker; and
a stress circuit fabricated on the same semiconductor
wafer as the dielectric regions and operable to stress at least one
of the dielectric regions internally within the semiconductor
wafer for assessing dielectric reliability without the influence of
an external circuit.
On appeal, the Examiner maintains the following rejections under
35 U.S.C. § I03(a):
1. claims 1-3, 5, 6, 13, 15, 16, 18-21, 23, and 27-29 over the
combination of Kerber (US 2007/0252611 Al, pub. Nov. 1, 2007)
and Tickle (US 4,420,497, issued Dec. 13, 1983);
2. claims 4, 14, 22, and 26 over the combination of Kerber, Tickle,
and Doi (US 2014/0295172 Al, pub. Oct. 2, 2014);
3. claim 7 over the combination of Kerber, Tickle, and Wang (US
6,492,240 B 1, issued Dec. 10, 2002);
4. claims 8-12, 24, and 25 over the combination of Kerber, Tickle,
and Emira (US 2014/0300409 Al, pub. Oct. 9, 2014); and
5. claim 17 over the combination of Kerber, Tickle, and Poindexter
(US 2014/0184262 Al, pub. July 3, 2014).
The complete statement of the rejections appear in the Final Action.
(Final Act. 2-16.)
2
Appeal2017-008799
Application 14/151,528
OPINI0N2
The Examiner finds Kerber discloses all the features of claim 1 except
the feature of dielectric regions of different thicknesses. (Final Act. 2-3.)
The Examiner finds Tickle discloses dielectric regions of different
thicknesses. (Final Act. 3; Tickle col. 3, 11. 5-10, Figs. la and lb.) The
Examiner concludes:
[I]t would have been obvious to one of ordinary skill in the art
before the filing date of the claimed invention to have modified
Kerber so that the dielectric regions have different thicknesses,
some of the dielectric regions being thinner and other ones of
the dielectric regions being thicker as taught by Tickle. This
would have been done in order to test the dielectric strength of
the different regions or layers as taught by Tickle at col. 3,
11. 1-17.
(Final Act. 3.)
Appellant argues Tickle fails to teach or disclose purposefully
creating a dielectric layer of different thicknesses as claimed. (App. Br. 8-
10.) Appellant argues Tickle is directed to repairing defects by forming a
self-healing oxide plug in a defective dielectric area by immersing the
subject wafer in a liquid electrolyte and applying voltage to the immersed
wafer. (App. Br. 9-10.) Appellant argues the differing thickness of oxide
plug 13B in Figure lb is merely an unplanned result of the purposeful
formation of an oxide plug to seal a defective area of Tickle' s dielectric
layer. (App. Br. 10.) For the above reasons, Appellant argues there is no
motivation to modify Kerber in view of Tickle. (App. Br. 10.)
2 We limit our discussion to independent claims 1 and 21.
3
Appeal2017-008799
Application 14/151,528
In response to Appellant's argument, the Examiner states:
Tickle is relied upon simply for a teaching of dielectric regions
of different thicknesses, a feature clearly taught by the reference
(Tickle at col. 3, 11. 5-12). For example, Tickle discloses that a
dielectric region having different thickness may form as a result
of latent pinholes, cracks and microscopic areas of low
breakdown (Tickle at col. 1, 11. 67-68) and that these areas are
tested by applying a voltage (Tickle at col. 2, 11. 5---6). That is,
Tickle discloses "dielectric regions of different thicknesses."
(Ans. 5.)
We agree with Appellant that the Examiner has failed to provide
adequate reasons to modify the semiconductor structure of Kerber in view of
Tickle. The Examiner points to column 3 of Tickle as exemplifying a
semiconductor structure with an uneven surface. (Final Act. 3.) Tickle is
directed to methods for locating and repairing latent pinholes, cracks, and
microscopic areas of low breakdown voltage in dielectric layers prior to
completion of the devices. (Tickle col. 1, 11. 7-12.) Tickle discloses latent
defects in the dielectric layer are repaired by the formation of additional
dielectric material within the damaged area. (Tickle paragraph bridging
cols. 1-2.) The Examiner has failed to direct us to evidence that the
problems of latent pinholes, cracks, and microscopic areas of low
breakdown voltage in dielectric layers are a problem or concern in Kerber.
The Examiner has also failed to direct us to evidence that the repair
techniques as suggested by Tickle would have been suitable for a
semiconductor wafer that includes a dielectric test structure including a
voltage line, a control line, and a plurality of test devices connected in
parallel to the voltage line and the control line as described by Kerber.
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Appeal2017-008799
Application 14/151,528
For the foregoing reasons and those presented by Appellant we
reverse the appealed rejections.
DECISION
The Examiner's appealed rejections of claims 1-29 are reversed.
REVERSED
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