Ex Parte Riley

Board of Patent Appeals and Interferences

Sep 20, 2010

10444451 (B.P.A.I. Sep. 20, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte DWIGHT D. RILEY
____________________

Appeal 2009-004150
Application 10/444,4511
Technology Center 2100
____________________

Before JOSEPH L. DIXON, JEAN R. HOMERE, and JAY P. LUCAS,
Administrative Patent Judges.

LUCAS, Administrative Patent Judge.

DECISION ON APPEAL2

1 Application filed May 23, 2003. The real party in interest is Hewlett
Packard Development Co., LP.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

Appeal 2009-004150
Application 10/444,451

STATEMENT OF THE CASE
Appellant appeals from a final rejection of claims 1 to 16 under
authority of 35 U.S.C. § 134(a). The Board of Patent Appeals and
Interferences (BPAI) has jurisdiction under 35 U.S.C. § 6(b).

We reverse.

Appellant’s invention relates to a system and method for increasing
the speed of a bus in an electronic circuit in which various devices may be
addressed. The invention checks the correctness of an address of a message
at the same time that any error in the address is being corrected. In the
words of Appellant:
In accordance with various bus protocols, a
transaction may be provided from an initiator
device to at least one of various target devices on a
bus or interconnect. Such protocols may include
peripheral component interconnect ("PCI") or PCI-
X. Each device may decode the transaction to
determine if the transaction is intended for that or
another device. If the transaction is intended for
that device, the device may claim and process the
transaction. If the transaction is not intended for
that device, the device does not claim the cycle.
Instead, another device may successfully decode
and claim the transaction.
. . . .
As disclosed herein, an interface for a device
adapted to couple to an interconnect may comprise
decode and error check logic and a plurality of
decode logic units. The decode and error check
logic may receive error check bits and a target
address from the interconnect and may determine
whether the target address was received in error.
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Application 10/444,451

At least one of the decode logic units also may
receive the error check bits and correct the target
address using the error check bits in parallel with
the decode and error check logic determining
whether the target address was received in error.

(Spec. 1, ¶ [0001]; Abstract, Spec 11).
The following illustrates the claims on appeal:
Claim 1:
1. An interface for a device adapted to couple
to an interconnect, comprising:

decode and error check logic that receives
error check bits and a target address
from said interconnect and determines
whether the target address was
received in error; and

a plurality of decode logic units that each
receive the target address;

wherein at least one of said decode logic
units also receives the error check bits and
corrects the target address using the error
check bits in parallel with the decode and
error check logic determining whether the
target address was received in error.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Chin US 6,272,651 B1 Aug. 07, 2001
Maciver US 2002/0013929 A1 Jan. 31, 2002

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Appeal 2009-004150
Application 10/444,451

REJECTIONS
The Examiner rejects the claims as follows:

R1: Claims 1 to 16 stand rejected under 35 U.S.C. § 102(b) for being
anticipated by Maciver. The Examiner explains the rejection in detail for
claims 1 to 5 and 12 to 14, so we will interpret the rejection as applying to
those claims (Ans. 3 to 5).
R2: Claims 6 to 11 stand rejected under 35 U.S.C. § 103(a) for being
obvious over Maciver in view of Chin. The Examiner explains the rejection
in detail for claims 6 to 11, 15 and 16, so we will interpret the rejection as
applying to those claims (Ans. 5 to 9)

We will review the rejections in the order argued.
ISSUE
The pivotal issue before us is whether Appellant has shown that the
Examiner erred in rejecting the claims under 35 U.S.C. § 102(b) and
35 U.S.C. § 103(a). The issue specifically turns on whether Maciver teaches
a logic unit that corrects a target address in parallel with determining
whether the target address was received in error.
FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
1. Appellant has invented a system for sending transactions to devices on a
bus, such as a PCI-X bus, with compatible devices attached to it (Spec. ¶
[0012]). The invention relates to the “front end” of such devices, which
is responsible for accepting transactions related to that particular device
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Application 10/444,451

(Id.). As addressing errors for a messages sometimes occur, the
invention works on detecting an error at the same time that it is working
on correcting it, to save time and speed up the process (¶ [0014]). Thus if
an error is found, the “front end” logic has already started the process of
correcting it (Id.).
2. The Maciver reference discloses identifying and correcting errors in data
sent from one component in a computer to another (¶ [0028]). The data
may be an address (¶¶ [0022], [0025]). Referring to Maciver’s Figure 2
(below), parity checker #212 determines if an error exists in the data, and
sends check bits indicative of the presence of the error to error correction
circuit #214 (¶ [0041]). Error correction circuit #214 corrects the error
and sends it on to data receiver #216. (¶[0030]).
3. Figure 2 of Maciver:

A Block Diagram of Maciver’s system.
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Appeal 2009-004150
Application 10/444,451

PRINCIPLES OF LAW

Appellants have the burden on appeal to the Board to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a
rejection [under § 103] by showing insufficient evidence of prima facie
obviousness or by rebutting the prima facie case with evidence of secondary
indicia of nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355
(Fed. Cir. 1998)).

In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citation omitted).
Anticipation of a patent claim requires a finding that the claim
at issue ‘reads on’ a prior art reference. In other words, if
granting patent protection on the disputed claim would allow
the patentee to exclude the public from practicing the prior art,
then that claim is anticipated, regardless of whether it also
covers subject matter not in the prior art.

Atlas Powder Co. v. IRECO, Inc., 190 F.3d 1342, 1346 (Fed. Cir. 1999)
(internal citations omitted).

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Appeal 2009-004150
Application 10/444,451

ANALYSIS
Arguments with respect to the rejection
of claims 1 to 16
under 35 U.S.C. § 102(b) and 35 U.S.C. § 103(a) [R1, R2]

The Examiner has rejected all of the claims for being anticipated by
Maciver alone, or for being obvious over Maciver in view of Chin.
Appellant argues with respect to claim 1 that “Nowhere does Maciver teach
or even suggest that logic corrects the target address in parallel with or
concurrently with logic determining whether the target address was
received in error.” (Brief 8, top).
We agree with Appellant. Paragraph 41 of the reference clearly states
that “the parity checker checks the received data and parity and determines
whether there is an error and the location of the error if one is present.”
(Maciver ¶ [0041]). The parity checker then produces check bits, C1, C2
and C4 in the example (¶ [0033]). Thereafter, the error correction circuit
#214 combines the check bits with the received data to correct the error of
the data, if any (¶ [0030]).
A limitation of representative claim 1 (and, in one form or another, of
the other independent claims) requires that a logic unit corrects the target
address [data] in parallel with the determining of whether the target address
was in error. Clearly in Maciver the process is serial, not in parallel, as the
“determining” is done before generating the check bits, and before
correcting the errors, as demonstrated just above.
Appellant has thus found error in the rejections of such a nature as to
apply to all the claims.
Appellant’s other contentions have not been reviewed, as this error is
dispositive of the appeal.
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Appeal 2009-004150
Application 10/444,451

CONCLUSIONS OF LAW
Based on the findings of facts and analysis above, we conclude that
Appellant has shown that the Examiner erred in rejecting claims 1 to 16.

DECISION
We reverse the Examiner’s rejection of claims 1 to 16.
REVERSED

peb

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