Ex Parte Richter et al

Patent Trial and Appeal Board

Nov 27, 2013

12017175 (P.T.A.B. Nov. 27, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/017,175 01/21/2008 Ralf Richter 2162.155800/DE0971 5890
10742 7590 11/27/2013
GLOBALFOUNDRIES INC.
c/o Williams, Morgan & Amerson
10333 Richmond , Suite 1100
Houston, TX 77042
EXAMINER
SUN, YU-HSI DAVID
ART UNIT PAPER NUMBER
2895
MAIL DATE DELIVERY MODE
11/27/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL
AND APPEAL BOARD
____________

Ex parte RALF RICHTER, ANDY WEI,
and ROMAN BOSCHKE
____________

Appeal 2011-007654
Application 12/017,175
Technology Center 2800
____________

Before PETER F. KRATZ, BEVERLY A. FRANKLIN, and
MARK NAGUMO, Administrative Patent Judges.

FRANKLIN, Administrative Patent Judge.

DECISION ON APPEAL

Appellants appeal under 35 U.S.C. § 134 from the Examiner's
rejection of claims 1, 3-7, 9, and 11-17. We have jurisdiction under 35
U.S.C. § 6.
STATEMENT OF THE CASE
Claim 1 is representative of the subject matter on appeal and is set
forth below:
1. A method, comprising:
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forming a first stress-inducing layer above a first transistor formed
above a substrate, said
first stress-inducing layer generating a first type of stress;
forming a second stress-inducing layer above a second transistor, said
second stress- inducing layer generating a second type of stress other than
said first type of stress;
forming a third dielectric layer above said first and second transistors
and in direct contact with said first and second stress-inducing layers, said
third dielectric layer having an internal stress level above said first transistor
that is less than that of said first and second stress-inducing layers;
forming an interlayer dielectric material above said first and second
transistors; and
forming contact openings in said interlayer dielectric material by
using said third dielectric layer as an etch stop material for the etching of
said interlayer dielectric material.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Burbach US 2006/0046400 A1 Mar. 2, 2006
Kammler US 2006/0246641 A1 Nov. 2, 2006
Chao US 2006/0267106 A1 Nov. 30, 2006
Hsu US 2007/0235823 A1 Oct. 11, 2007

THE REJECTIONS

1. Claims 1, 3-7, 11 and 13-17 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Hsu in view of Burbach.

2. Claim 9 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Burbach in view of Kammler.
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3. Claim 12 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Hsu in view of Burbach and further in view of Chao.

ANALYSIS

The Examiner relies upon Hsu for teaching certain aspects of claim 1,
but recognizes that Hsu does not disclose a second stress-inducing layer
above the second transistor, said second stress-inducing layer generating a
second type of stress, wherein said second type of stress is different from
said first type of stress. Ans. 5. The Examiner relies upon Burbach for
teaching this aspect of the claimed subject matter. The Examiner finds that
Figure 2e of Burbach discloses a first stress- inducing layer (203c) above a
first transistor (4) said first stress-inducing layer generating a first type of
stress (paragraph 47), and a second stress-inducing layer (201) above a
second transistor (3), said second stress-inducing layer generating a second
type of stress (paragraph 36) of other than said first type of stress (paragraph
47). Ans. 5. The Examiner concludes that it would have been obvious to
have employed first and second stress-inducing layers in the claimed manner
in view of Burbach for the purpose of providing stresses that can enhance
different kinds of transistors within the same device. Ans. 5-6.
The Examiner also recognizes that Hsu does not teach a third
dielectric layer having an internal stress level that is less than that of said
first and second stress-inducing layers. The Examiner reasons that there are
a limited number of possibilities for the relative stress levels of such a layer,
i.e., that the third dielectric layer can have an internal stress level that is
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either less than, equal to, or greater than that of said first and second stress-
inducing layers. Ans. 6. The Examiner concludes that therefore it would
have been obvious to have selected from among these three choices to arrive
at the claimed subject matter in order to make a device meeting various
design constraints and also for the purpose of choosing from a finite number
of identified, predictable solutions, with a reasonable expectation of success
Id., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385
(2007).
At the bottom of page 7 of the Brief, Appellants explain that Hsu’s
layer 34 is the primary stress-inducing layer (Hsu, paras. [0036] –[0039]).
The Examiner does not dispute that Hsu’s layer 34 is the primary stress-
inducing layer. See Answer generally.
On page 2 of the Reply Brief, Appellants further explain that
Hsu shows two layers having the same stress type formed over NMOS
and PMOS transistors. Hsu states in [0036], "Preferably, dielectric
layer 32 has a thickness of between about 50 .ANG. and about 250
.ANG., and CESL 34 has a thickness of between about 300_.ANG.
and about 1500 .ANG." The Office argues that the layers of Burbach
may be substituted for the layer 32 of Hsu and it would be obvious for
form the layer 34 of Hsu to have a stress levels less than that of the
underlying layers.
Applicants assert that this construction is arbitrary and in contrast with
the express teachings of Hsu. Hsu clearly teaches that upper the layer
34 is the primary stressed layer. The layer 32 is optional and has a
thickness that is significantly less than that of the layer 34. In
paragraphs [0037]-[0040], Hsu also indicates that the upper contact
etch stop layer is thick, while the underlying layer is thin.
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Appellants conclude that in view of the relative thicknesses of layers
32 and 34 of Hsu, and the teachings of Hsu that layer 34 is the primary
stress-inducing layer, there is no basis for the conclusion proffered by the
Examiner that the upper layer 34 would have a reduced stress compared to
the lower layer 32. Appellants submit that as suggested in para. [0043] of
Hsu, and as clearly illustrated in the Hsu’s Figures, the lower layer 32 serves
to reduce the aspect ratio to allow a thicker contact etch stop layer to be
provided. The thicker contact etch stop layer allows the stress level to be
increased and improve performance. Reply Br. 3.
In spite of this fact that Hsu teaches that layer 34 is the primary stress-
inducing layer, it is the Examiner’s position that it would have been obvious
to have chosen the stress level as claimed by Appellants (whereby the third
dielectric layer has an internal stress level, above the first transistor, that is
less than that of the first and second stress-inducing layers) because the
possible choices are only from among three: one that is less than, equal to, or
greater than that of said first and second stress-inducing layers. However,
this obvious to try rationale does not rise to the level of a prima facie case of
obviousness because the Examiner has not established, e.g., the existence of
“a design need or market pressure to solve a problem” or the existence of “a
finite number of identified, predictable solutions” such that “a person of
ordinary skill has good reason to pursue the known options within his or her
technical grasp.” KSR, 550 U.S. at 421. Moreover, the Examiner has not
convincingly established that replacing layer 32 of Hsu with Burbach’s two
separate stressed layers of different stresses is a substitution of art
recognized equivalents (Ans. 9-10). In order to rely on equivalence as a
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rationale supporting an obviousness rejection, the record must show that the
equivalency was recognized in the prior art.
In view of the above, we thus reverse Rejection 1. Because the other
applied references in the other rejections do not cure the deficiencies of Hsu
and Burbach, we also reverse Rejections 2 and 3.
CONCLUSIONS OF LAW AND DECISION
Each rejection is reversed.

REVERSED

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