Ex Parte Richards et al

Board of Patent Appeals and Interferences

Jan 23, 2012

11295105 (B.P.A.I. Jan. 23, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/295,105 12/06/2005 William R. Richards JR. 4134-43 7788
20792 7590 01/23/2012
MYERS BIGEL SIBLEY & SAJOVEC
PO BOX 37428
RALEIGH, NC 27627
EXAMINER
LI, MEIYA
ART UNIT PAPER NUMBER
2811
MAIL DATE DELIVERY MODE
01/23/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte WILLIAM R. RICHARDS, JR. and MIKE YEN-CHAO SHEN
____________________

Appeal 2010-001398
Application 11/295,105
Technology Center 2800
____________________

Before HOWARD B. BLANKENSHIP, JEAN R. HOMERE, and
THU A. DANG, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

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Application 11/295,105

2
I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-16, 23, and 24 (App. Br. 2). Appellants are not appealing the
Examiner’s rejections of claims 23 and 24, but note that these claims are
pending (App. Br. 2). The Board has no jurisdiction as to non-appealed
claims, and we consider claims 23 and 24 cancelled and not before us for
review. The Examiner has the authority to cancel the non-appealed claims
23 and 24. See Ex parte Ghuman, 88 USPQ2d 1478, 1480 (BPAI 2008)
(precedential). Claims 17-22 have been canceled (App. Br. 2). We have
jurisdiction of claims 1-16 under 35 U.S.C. § 6(b).
We affirm.

A. INVENTION
Appellants’ invention relates to a strained Silicon (Si)-on-Silicon-
Germanium (SiGe) Fermi-Field Effect Transistor (FET) having dopings that
realize ideal Fermi-FET characteristics, such as, a nearly zero electrical field
in the gate insulator; wherein, the doping of the strained silicon channel, the
doping of the substrate and/or the depth of the strained silicon channel are
configured to produce nearly zero vertical electric field in the gate insulating
layer and in the strained silicon channel surface at a threshold voltage of the
field effect transistor (Abstract; Spec. 9:25-35)
B. ILLUSTRATIVE CLAIM
Claim 1 is exemplary:
1. A field effect transistor comprising:

a strained silicon channel in a substrate;

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source/drain regions in the substrate at opposite ends of the
strained silicon channel;

a gate insulating layer on the strained silicon channel, wherein
doping of the strained silicon channel, doping of the substrate and/or a
depth of the strained silicon channel are configured to produce nearly
zero vertical electric field in the gate insulating layer and in the
strained silicon channel adjacent thereto at a threshold voltage of the
field effect transistor; and

a gate on the gate insulating layer that is configured to provide a
gate work function that is close to a mid-bandgap of silicon.

C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Vinal US 5, 151, 759 Sept. 29, 1992
Bulucea US 5, 952, 701 Sept. 14, 1999
Murthy US 6, 373, 112 B1 Apr. 16, 2002
Isaacson US 2005/0280081 A1 Dec. 22, 2005

Claims 1-16 stand rejected under 35 U.S.C. 112, second paragraph, as
being indefinite for failing to particularly point out and distinctly claim the
subject matter which Appellants regard as the invention.
Claims 1-3, 5-12, and 14-16 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Isaacson in view of Vinal.
Claims 4 and 13 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Isaacson in view of Vinal and Murthy.

Appeal 2010-001398
Application 11/295,105

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II. ISSUES
The dispositive issues before us are whether the Examiner has erred in
determining that:
1. the term “and/or” renders the claim indefinite for failing to
particularly point out and distinctly claim the subject matter which
Appellants regard as the invention(claim 1, emphasis added); and
2. the combination of Isaacson and Vinal would have taught or fairly
suggested a field effect transistor comprising :
a strained silicon channel in a substrate;
. . . .
a gate insulating layer on the strained silicon channel,
wherein doping of the strained silicon channel, doping of the
substrate and/or a depth of the strained silicon channel are
configured to produce nearly zero vertical electric field in the
gate insulating layer and in the strained silicon channel
adjacent thereto at a threshold voltage of the field effect
transistor.

(Claim 1, emphasis added).

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Isaacson
1. Isaacson discloses a transistor 1000 that “includes a gate
contact 1051, source and drain contacts 1052, 1053, such as silicide contacts,
a gate dielectric layer 1054, an unstrained silicon first layer 1010, an
unstrained or strained SiGe intermediate layer 1030 bonded directly to the
unstrained silicon layer 1010, and a tensilely strained silicon second layer
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1020 on the unstrained or strained SiGe intermediate layer 1030” which
overlays an unstrained Si Substrate 1010 (Fig.10;¶[0109]); wherein, the gate
dielectric 1054 is formed on the tensilely strained layer 1020 (¶[0114]).
2. The substrate may also incorporate buried insulating layers, in
the manner of the Silicon-on-Insulator (SOI) wafer (¶ [0007]).
Vinal
3. Vinal discloses a SOI FET having a gate insulating layer;
wherein, at least one of the source doping, source depth, drain doping, drain
depth, channel substrate doping, channel substrate depth, channel doping,
and channel depth being selected to produce zero static electric field
perpendicular to the surface between a channel substrate and the adjacent
gate insulating layer (Abstract; col. 38, ll.17-26).

IV. ANALYSIS
Claims 1-16
The Examiner rejects claims 1-16 under 35 U.S.C. § 112, second
paragraph, as being indefinite for failing to particularly point out and
distinctly claim the subject matter which Appellants regard as the invention,
pertaining to the recitation in claim 1 of “doping of the strained silicon
channel, doping of the substrate and/or a depth of the strained silicon
channel” (Final Rej. 2, emphasis added).
Appellants contend that “[t]he term ‘and/or’ is a well-defined logical
construct” “to the extent that ‘or’ or ‘and/or’ is an alternative expression,
such form of expression is expressly sanctioned by MPEP § 2173.01” (App.
Br. 6). Appellants assert that “this term is widely used in claims and
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certainly is not indefinite, especially when the term is explicitly defined in
the present specification” (id.).
We agree with Appellants that the term “and/or” constitutes an
alternative expression. In reaching this conclusion, we find the term
“and/or” simply means that the recited elements before and after the term
(i.e., the elements noted above) are optional. That is, the limitation merely
recites alternatives which may or may not be present in the claimed
invention—alternatives that ordinarily skilled artisans can readily ascertain.
Reciting optional limitations does not, without more, render claims
indefinite. See Ex parte Cordova, 10 USPQ2d 1949, 1950 (BPAI 1987)
(“[T]he use of the alternative expression “optionally” in the rejected claims
does not obfuscate the subject matter [A]ppellants regard as their
invention”); Ex parte Wu, 10 USPQ2d 2031 (BPAI 1989) (finding no
difficulty in determining the scope of a claim reciting composition
consisting of three components and, optionally, a fourth component); Ex
parte Schonauer, No. 2002-1992, 2002 WL 33950061, at *2 (BPAI Nov. 25,
2002) (non-precedential) (“The examiner has not explained, and it is not
apparent, why the fact that the claims encompass methods in which the
components following ‘optionally’ can be either present or absent renders
the claims indefinite”).
Accordingly, we conclude that claim 1 does reasonably apprise those
skilled in the art of its scope. Because we conclude that there are no
ambiguities with respect to claim 1 and thus claims 2-16 depending
therefrom, we reverse the rejection of claims 1-16 under 35 U.S.C. § 112,
second paragraph.
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Claims 1-3, 5-12, and 14-16
Appellants do not provide separate arguments with respect to
independent claims 1, 8, and 11 (App. Br. 6). Appellants do not provide
arguments with respect to dependent claims 2, 3, 5-7, 9, 10, 12, and 14-16
(id.). Accordingly, we select claim 1 as being representative of the claims.
See 37 C.F.R. § 41.37(c)(1)(vii).
Appellants contend that “Vinal relates to a Fermi-threshold silicon-on-
insulator (SOI) field effect transistor,” and the “SOI technology [disclosed in
Vinal] and strained silicon technology [disclosed in Isaacson] are not the
same” (App. Br. 7). Appellants argue that “Isaacson explicitly teaches away
from the use of SOI technology” because Issacson discloses that “an
alternative to a Si1-xGex -based substrate, strained silicon can be provided on
an oxide layer of a substrate;” yet, “[t]he presence of the oxide layer …
forces process modifications” (App. Br. 9). Appellants argue that “there are
unexpected results when combining a Fermi-FET design with a strained
silicon channel” because “performance gains in regular transistors may be
rather limited when using strained silicon;” yet, “[i]n contrast, a Fermi-FET
may enjoy significantly more benefit from strained silicon technology”
(App. Br. 10).
However, the Examiner finds that Appellants’ first argument is not
persuasive because “the Examiner relied on Vinal to teach only the nearly
zero vertical electric field, not to teach the strained silicon technology or SOI
technology” and “relied upon Issacson to teach the strained silicon
technology” (Ans.11). The Examiner finds further that the disclosure in
Isaacson “is not necessarily a teaching away from the use of SOI technology,
especially since Issacson states that if the oxide is present, the process can
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Application 11/295,105

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We find that Issacson’s tensilely strained silicon second layer
comprises a “strained silicon channel in a substrate” (claim 1). Further, we
find that Issacson’s gate dielectric layer comprises a gate insulating layer
that is formed overlaying the strained silicon channel (FF1). That is, we find
that “a strained silicon channel in a substrate” and “a gate insulating layer on
the strained silicon channel” (claim 1) reads on Issacson’s tensilely strained
silicon second layer and gate dielectric layer, respectively.
In addition, Vinal discloses a SOI FET having a gate insulating layer;
wherein, the channel substrate doping, the channel substrate depth, the
channel doping and the channel depth are selected to produce a zero static
electric field perpendicular to the surface between a channel substrate and
the adjacent gate insulating layer (FF 3). We find that Vinal’s selection of
the channel substrate doping, the channel substrate depth, the channel
doping and the channel depth to produce zero static electric field
perpendicular to the surface between a channel substrate and the adjacent
gate insulating layer to be “doping of the strained silicon channel, doping of
the substrate and/or a depth of the strained silicon channel . . . to produce
nearly zero vertical electric field in the gate insulating layer and in the
strained silicon channel adjacent thereto at a threshold voltage of the field
effect transistor” (claim 1).
We agree with the Examiner’s finding that the Appellants’ argument
that the “SOI technology [disclosed in Vinal] and strained silicon technology
[disclosed in Isaacson] are not the same” (App. Br. 7) is non-persuasive,
since “the Examiner relied on Vinal to teach only the nearly zero vertical
electric field, not to teach the strained silicon technology or SOI technology”
(Ans. 11).
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We find that the combination of Isaacson and Vinal would have
suggested providing:
a strained silicon channel in a substrate;
. . . .
a gate insulating layer on the strained silicon channel,
wherein doping of the strained silicon channel, doping of the
substrate and/or a depth of the strained silicon channel are
configured to produce nearly zero vertical electric field in the
gate insulating layer and in the strained silicon channel adjacent
thereto at a threshold voltage of the field effect transistor; . . .

as specifically required by claim 1.
Though Appellants also contend that the combination “teaches away”
(App. Br. 9), our reviewing court has held that “‘[a] reference may be said to
teach away when a person of ordinary skill, upon [examining] the reference,
would be discouraged from following the path set out in the reference, or
would be led in a direction divergent from the path that was taken by the
applicant.’” Para-Ordnance Mfg., Inc. v. SGS Importers Int’l., Inc., 73 F.3d
1085, 1090 (Fed. Cir. 1995) (quoting In re Gurley, 27 F.3d 551, 553 (Fed.
Cir. 1994)).
Appellants have identified no express support for a direction
divergent from the claimed invention since the recitation from Isaacson
presented by Appellants focuses upon the disadvantages of substituting an
oxide layer for a relaxed Si-Ge buffer (App. Br. 9), and not the
disadvantages of incorporation of buried insulating layers using SOI
technology. Further, Issacson discloses that the substrate may also
incorporate buried insulating layers, in the manner of an SOI wafer (FF 2).
Here, the Appellants appear to have viewed the reference from a different
perspective than the Examiner. The issue here is not whether Isaacson
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teaches SOI technology but rather whether a person of ordinary skill, upon
reading Isaacson, would be discouraged from using the step of selecting the
channel doping, substrate doping, or channel depth to produce a zero static
electric field perpendicular to the surface between a channel substrate and
the adjacent gate insulating layer as taught by Vinal.
Regarding the Appellants’ argument that the results are unexpected,
our reviewing court has held that “[o]ne way for a patent applicant to rebut a
prima facie case of obviousness is to make a showing of ‘unexpected
results,’ i.e., to show that the claimed invention exhibits some superior
property or advantage that person of ordinary skill in the relevant art would
have found surprising or unexpected.” In re Soni, 54 F.3d 746, 750 (Fed.
Cir. 1995).
In In re Dillon, 919 F.2d 688, 696 (Fed. Cir. 1990), the Federal
Circuit noted:

In brief, the cases establish that if an [E]xaminer
considers that he has found prior art close enough to the
claimed invention to give one skilled in the relevant chemical
art the motivation to make close relatives . . . of the prior art
compound(s), then there arises what has been called a
presumption of obviousness or a prima facie case of
obviousness. In re Henze, 181 F.2d 196, 37 CCPA 1009, 85
USPQ 261 (CCPA 1950); In re Hass, 141 F.2d 122, 127, 130,
31 CCPA 895, 60 USPQ 544, 548, 552 (CCPA 1944). The
burden then shifts to the A]pplicant, who then can present
arguments and/or data to show that what appears to be obvious,
is not in fact that, when the invention is looked at as a whole.
In re Papesch, 315 F.2d 381, 50 CCPA 1084, 137 USPQ 43
(CCPA 1963).

We have reviewed the record and agree with the Examiner’s finding
that Appellants have not provided evidence of the unexpected results.
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Further, Appellants argue that the Specification discloses that strained-Si
mobility enhancement is more beneficial in the Fermi-FET as opposed to n
and p-channel MOSFET devices, since higher dopings are used for these
MOSFET devices and lighter dopings are typically used in Fermi-FETs
(Spec. 13, l. 22- 14, l. 13). However, this recitation does not support an
unexpected result, since it merely discloses that the effects of strained-Si
mobility enhancement on Fermi-FETs as opposed to MOSFET devices
differ which would be expected. Moreover, this recitation serves to support
an expected result of strained-Si mobility enhancement in a Fermi-FET,
since a lighter doping should exhibit a greater degree of relative hole
mobility enhancement for p-channel Fermi-FETs. Therefore, we find that
the presumption of unpatentability is not overcome.
The Supreme Court has stated that “[t]he combination of familiar
elements according to known methods is likely to be obvious when it does
no more than yield predictable results.” KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398, 416 (2007).
Thus, we find no error in the Examiner’s finding that the combination
of Isaacson’s transistor (gate insulating layer on top of a strained silicon
channel within a substrate) with channel/substrate doping and channel depth
selection step for zero static electric field perpendicular to the surface
between a channel substrate and the adjacent gate insulating layer, as
disclosed in Vinal, produces zero vertical electric field in the gate insulating
layer and in the strained silicon channel which would be obvious (Ans. 5;
FF1 and 3).
Accordingly, we find that Appellants have not shown that the
Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a) over Issacson
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in view of Vinal; and independent claims 8 and 11 and claims 2, 3, 5-7, 9,
10, 12, and 14-16 depending from claims 1, 8, and 11 which have been
grouped therewith.
Claims 4 and 13
Appellants argue that claims 4 and 13 is patentable over the cited prior
art for the same reasons asserted with respect to claim 1 (App. Br. 11).
As noted supra, however, we find that the combination of Isaacson
and Vinal discloses all the features of claim 1. We therefore affirm the
Examiner’s rejection of claims 4 and 13 under 35 U.S.C. § 103 for the same
reasons expressed with respect to parent claims 1 and 11, supra.

V. CONCLUSION AND DECISION
The Examiner’s rejection of claims 1-16 under 35 U.S.C. § 112,
second paragraph is reversed. However, the Examiner’s rejection of claims
1-16 under 35 U.S.C. § 103(a) is affirmed.
Because we have affirmed at least one ground of rejection with
respect to each claim on appeal, the Examiner’s decision is affirmed. See
37 C.F.R. § 41.50(a)(1).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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