11513087 (P.T.A.B. Jul. 29, 2013)

Ex Parte Rasmussen et al

Patent Trial and Appeal BoardJul 29, 2013

11513087 (P.T.A.B. Jul. 29, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte PHILLIP RASMUSSEN and CHARLES SNODGRASS ____________ Appeal 2011-001965 Application 11/513,087 Technology Center 2100 ____________ Before ST. JOHN COURTENAY III, CARLA M. KRIVAK, and ANDREW J. DILLON, Administrative Patent Judges. DILLON, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 1-42. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. STATEMENT OF THE CASE Appellants’ invention is directed to an integrated circuit tester that “utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with sub-instruction repeats.” See Specification 27, Abstract. Appeal 2011-001965 Application 11/513,087 2 Claims 1 and 24 are illustrative, with key disputed limitations emphasized: 1. A method of operating an integrated circuit tester, comprising: executing a command sequence of a test on an integrated circuit tester containing two or more Algorithmic Pattern Generators (APGs) by executing the test command sequence in parallel on the two or more APGs, wherein each APG of the two or more APGs generates a single sub-instruction of a test instruction during each APG clock cycle; coupling the outputs of the two or more APGs to one or more integrated circuit devices under test (DUTs), wherein only one sub-instruction is coupled to the one or more DUTs during a DUT clock cycle and where each APG clock cycle contains two or more DUT clock cycles; and repeating a selected sub-instruction of a single APG by coupling the selected sub-instruction of that single APG to the one or more DUTs over two or more consecutive DUT clock cycles. 24. An integrated circuit tester, comprising: two or more Algorithmic Pattern Generators (APGs), wherein the two or more APGs are adapted to execute the command sequences of a test in parallel; and a multiplexer circuit coupled to the two or more APGs, wherein the multiplexer circuit is adapted to couple an output of a selected APG to an integrated circuit device under test (DUT) over two or more consecutive clock periods of a clock coupled to the DUT. The Examiner relies on the following as evidence of unpatentability: Kawaguchi US 4,905,183 Feb. 27, 1990 Satoh US 5,127,010 Jun. 30, 1992 Appeal 2011-001965 Application 11/513,087 3 Fujisaki US 6,006,349 Dec. 21, 1999 Arimoto US 6,400,625 B2 Jun. 4, 2002 THE REJECTIONS 1. The Examiner rejected claims 1, 3-7, 9-12, 14-16, 18-25, 27-33, and 35-42 under 35 U.S.C. §103(a) as unpatentable over Fujisaki and Satoh. Ans. 4-19.1 2. The Examiner rejected claim 8 under 35 U.S.C. §103(a) as unpatentable over Fujisaki, Satoh, and Kawaguchi. Ans. 20. 3. The Examiner rejected claims 2, 13, 17, 26, and 34 under 35 U.S.C. §103(a) as unpatentable over Fujisaki, Satoh, and Arimoto. Ans. 20-22. ISSUES Based upon our review of the record, the arguments proffered by Appellants, and the findings of the Examiner, we find the following issues to be dispositive of the claims on appeal: Under § 103, has the Examiner erred by finding Fujisaki and Satoh, collectively, show or suggest “repeating a selected sub-instruction of a single APG by coupling the selected sub-instruction of that single APG to the one or more DUTs over two or more consecutive DUT clock cycles” as set forth in claim 1, or, that Fujisaki and Satoh, collectively, show or suggest a multiplexer circuit “adapted to couple an output of a selected APG to an 1 Throughout this opinion, we refer to the Appeal Brief filed September 7, 2010; the Examiner’s Answer mailed October 28, 2010; and the Reply Brief filed October 29, 2010. Appeal 2011-001965 Application 11/513,087 4 integrated circuit device under test (DUT) over two or more consecutive clock periods of a clock coupled to the DUT” as set forth in claim 24? ANALYSIS We have reviewed the Examiner’s rejections in light of Appellants’ contentions in the Appeal Brief (App. Br. 11-22) and the Reply Brief (Reply Br. 2-3) that the Examiner has erred. We agree with Appellants’ conclusions for the reasons we set forth below. The Examiner finds Fujisaki discloses a method of operating an integrated circuit tester which includes two or more APGs each generating a single sub-instruction of a test instruction during each APG clock cycle. The outputs of the two or more APGs are coupled to one or more DUTs during a DUT clock cycle. Ans. 4-5. While admitting Fujisaki does not explicitly disclose coupling a selected sub-instruction of a single APG to a DUT over two consecutive DUT clock cycles, and citing Satoh for that purpose, noting that Satoh, in an analogous art, discloses an instruction coupled to a DUT over two consecutive DUT clock cycles, the Examiner finds one of ordinary skill in the art would have been motivated to generate the repeated pattern of Satoh with the high-speed pattern generation of Fujisaki. Ans. 5 (citations omitted). Appellants argue, inter alia, the Examiner’s proposed combination of Satoh’s pattern generator with the teachings of Fujisaki would result in either the high speed pattern signal of Fujisaki “having the same value for two consecutive DUT clock cycles, or the output of one of Fujisaki’s sub- pattern generating parts 120A-120D having the same value for two Appeal 2011-001965 Application 11/513,087 5 consecutive clock cycles of that sub-pattern generating part.” App. Br. 18- 19. Consequently, Appellants argue a sub pattern generating part (120A- 120D) of Fujisaki, as modified by the Examiner’s inclusion of Satoh’s teaching, would not have its output coupled to a DUT over two or more consecutive DUT clock cycles, as set forth in claim 1, and as similarly set forth in claim 24. Reply Br. 3. Based upon Appellants’ argument,2 we find the Examiner erred in rejecting claims 1-42 in that each independent claim substantially recites the limitation that the output of a selected APG is coupled to a DUT for two or more consecutive DUT clock cycles. CONCLUSION The Examiner erred in rejecting claims 1-42 under § 103. ORDER The Examiner’s decision rejecting claims 1-42 is reversed. REVERSED llw 2 We recognize Appellant’s arguments present additional issues. Some of the arguments presented by the additional issues are not persuasive. Nonetheless we are persuaded of error by the issue stated above, and as such we do not reach the additional issues as the issue stated above is dispositive of the appeal.