Ex Parte Rafacz et al

Patent Trial and Appeal Board

Feb 28, 2017

13653951 (P.T.A.B. Feb. 28, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/653,951 10/17/2012 Todd Rafacz 1458-120153 6890
109712 7590 03/02/2017
Advanced Micro Devices, Inc.
c/o Davidson Sheehan LLP
8834 North Capital of TX Hwy
Suite 100
Austin, TX 78759
EXAMINER
DEW AN, KAMAL K
ART UNIT PAPER NUMBER
2163
NOTIFICATION DATE DELIVERY MODE
03/02/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@ds-patent.com
AMD@DS-patent.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ADVANCED MICRO DEVICES, INC.1
Appeal 2016-005462
Application 13/653,951
Technology Center 2100
Before ELENI MANTIS MERCADER, CARL W. WHITEHEAD JR., and
ADAM J. PYONIN, Administrative Patent Judges.
MANTIS MERCADER, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1—7, 9-19, and 21—25, which constitute all the
claims pending in this application. We have jurisdiction under 35 U.S.C. §
6(b).
We affirm.
1 Todd Rafacz, Marius Evers, and Chitresh Narasimhaiah are named
inventors.
Appeal 2016-005462
Application 13/653,951
THE INVENTION
Appellant’s claimed invention is directed to a “processing system”
that both “monitors memory bandwidth available to transfer data from
memory to a cache” and “monitors a prefetching accuracy for prefetched
data” in order to determine whether “prefetching can be throttled”
(Abstract).
Independent claim 1, reproduced below, is representative of the
subject matter on appeal:
1. A method, comprising:
estimating an available memory bandwidth based
on a fullness of a cache buffer that buffers data provided
to and from a cache; and
throttling prefetching of data from the memory to
the cache based on the available memory bandwidth of the
memory and based on a prefetch accuracy of the
prefetching.
THE REJECTIONS
Claims 1—3, 6, 9, 13, 18, and 21—23 stand rejected under 35 U.S.C.
§ 102(b) as being anticipated by Tang (US 2011/0113199 Al; publ. May 12,
2011). Final Act. 12.
Claims 4, 5, 16, and 17 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Tang in view of Cai (US 2004/0268050 Al; publ.
Dec. 30, 2004). Final Act. 21.
Claims 7 and 19 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Tang in view of Morrow (US 2009/0019229 Al; publ.
Jan. 15, 2009). Final Act. 24.
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Application 13/653,951
Claims 10-12, 14, 15, 24, and 25 stand rejected under 35 U.S.C. §
103(a) as being unpatentable over Tang in view of Guthrie (US
2011/0161587 Al; publ. June 30, 2011). Final Act. 25.
ISSUES
The issues are whether the Examiner erred in finding that:
1. Tang discloses the “estimating an available memory bandwidth based
on a fullness of a cache buffer that buffers data provided to and from a
cache,” as recited in claim 1;
2. Tang discloses “estimating the available memory bandwidth
comprises estimating the available memory bandwidth based on both
the fullness of the cache buffer and a fullness of a memory buffer that
buffers data provided to and from the memory,” as recited in claim 9;
3. the combination of Tang and Guthrie disclose or suggest “temporarily
suspending the prefetching for a second period of time in response to
determining that the prefetch accuracy is below a third threshold,” as
recited in claim 11.
ANALYSIS
Claim 1
Appellant argues “Tang nowhere discloses a cache buffer that buffers
data provided to and from a cache in any manner” (App. Br. 4). Appellant
additionally contends “memory transactions in a queue are not the same as,
or equivalent to, data provided to a cache nor are such transactions data
provided from a cache” (App. Br. 5) and “one skilled in the art would
understand that the memory transaction queue referenced at para. [0037] of
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Tang stores transactions for system memory, and does not buffer data
provided to and from a cache” (App. Br. 6).
We do not agree with Appellant’s arguments. The Examiner finds,
and we agree, that Tang’s caches have buffers: Tang has “processor 100
which includes the components such as load and store buffers for the lower
level data cache (150, Fig. 1)” (Ans. 6 (citing Tang 120 and Fig. 1)); see
also Advisory Act. 2).2 Appellant does not challenge this finding in the
Reply Brief. See Reply Br. 2-A.
The Examiner additionally finds, and we agree, that in Tang,
bandwidth congestion may be measured... based on the fullness
(a number of outstanding transactions in an uncore pipeline as
tracked by a transaction counter associated with the uncore
pipeline) of the cache buffer that buffers data . . .
(Final Act. 12 (citing Tang 137) (emphasis omitted)). Indeed, “outstanding
transactions in a queue of the uncore—core components 211-214, cache
components 221-224, and MCIF 230—indicates the congestion level” (Tang
137).
Appellant is correct that the memory transaction queue does not buffer
data to and from a cache, however, the memory transaction queue (held in
MCIF 230 and/or IMC 231) measures congestion levels occurring in the
cache components 221—224, which measures congestion of the buffers.
2 Appellant correctly identifies deficiencies in the Examiner’s Answer in
which the “quotes throughout the Examiner’s Answer, both from para. 0043
and other passages in quotes, do not appear in Tang as quoted, but instead
appear to be the Examiner’s interpretation of Tang” (Reply Br. 2). We find
such deficiencies do not rise to reversible error, and our decision does not
rely on any Examiner finding in the Answer that is incorrectly presented as a
direct quote from a reference.
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Application 13/653,951
Tang additionally teaches the buffers are used to prefetch into a cache, as
Tang explicitly envisions the situation in which “a data element is prefetched
into a cache, such as a slice of a LLC managed by CSIL 221” (Tang 141
(cited at Final Act. 15 (regarding claim 6))). As a data element is prefetched
from a buffer into a cache managed by CSIL 221, a counter or queue depth
in the memory transaction queue is incremented to note the prefetch, and
MCIL 230 and/or IMC 231 measures the resulting congestion level.
Accordingly, we sustain the Examiner’s rejection of independent
claim 1 and independent claims 13 and 23 not separately argued (see App.
Br. 7), and the rejections of dependent claims 2—7, 14—19, 21, 22, 24, and 25
not separately argued with particularity (see App. Br. 8, 12).3
Claim 9
Appellant argues the Examiner erred because “Tang nowhere
discloses estimating an available memory bandwidth based on both of the
recited buffers” and “Tang nowhere teaches that the queue corresponds to or
includes a memory buffer that provides data to and from memory in any
manner” (App. Br. 7).
We do not agree with Appellant’s arguments. Again, Appellant’s
argument incorrectly asserts the memory transaction queue corresponds to a
buffer, whereas as shown above, the memory transaction queue is used to
calculate bandwidth congestion that occurs at the buffers. The Examiner
finds, and we agree, that a “transaction counter associated with the uncore
3 Should there be further prosecution, we note that the term “the available
memory bandwidth of the memory” appearing in claim 1 lacks antecedent
basis.
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pipeline” measures the fullness of the “cache and on-processor memory
interface module and load/store buffers” and “a number of busy pages in a
memory architecture and a number of outstanding transactions in a memory
interface pipeline” measures “the fullness of the memory buffer” (Final Act.
16 (citing Tang 137) (emphasis omitted)). Appellant does not address and
challenge the Examiner’s findings regarding either (1) the memory buffer
measured by the number of busy pages and outstanding transactions, or (2)
the cache buffers discussed above with respect to claim 1.
Accordingly, we sustain the Examiner’s rejections of dependent claim
9, and, for similar reasons, the rejections of independent claim 10 not
separately argued with particularity (see App. Br. 9), and dependent claim
12 not separately argued (see App. Br. 11).
Claim 11
Appellant argues the Examiner erred because “[njeither the cited
portions, nor any other portions of Guthrie, disclose or suggest employing
different thresholds of prefetch accuracy” and “Guthrie does not disclose or
suggest suspending prefetching for different periods of time in response to
determining a prefetch accuracy is below different thresholds” (App. Br. 10).
Appellant contends the cited paragraphs of Guthrie “teach only that
prefetching can be suspended and resumed in [sic] based on whether a
number of pending prefetch requests exceed a threshold” (App. Br. 10).
Regarding the number of thresholds used, Appellant’s argument is
unpersuasive of error because Appellant attacks Guthrie individually without
addressing the combination of references, and thus, fails to address the
Examiner’s findings. See In re Merck & Co., Inc., 800 F.2d 1091, 1097
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(Fed. Cir. 1986) (“Non-obviousness cannot be established by attacking
references individually where the rejection is based upon the teachings of a
combination of references”). The Examiner finds the claimed “third
threshold” encompasses Guthrie’s teaching that “IMC 206 determines
whether or not the number of pending prefetch requests is less than the
intermediate threshold” (Final Act. 28) (emphasis omitted) with the first and
second thresholds taught by Tang (see Final Act. 26—27).
Regarding the period of time of the suspension of prefetching, the
Examiner finds, and we agree, that Guthrie teaches the time period of a
suspension of prefetching may be related to the “rate of receipt” of the
pending prefetch requests (Final Act. 27 (citing Guthrie 17, 59)). One
skilled in the art would, at the time of invention, understand that a
suspension having a threshold tied to a rate could have a duration lasting
until the measured rate falls below the threshold. Such a time period would,
as taught by Guthrie, lower “lengthy demand memory access latencies”
(Final Act. 27 (citing Guthrie 17)).
Accordingly, we sustain the Examiner’s rejection of dependent claim
11.
CONCLUSION
The Examiner did not err in finding that:
1. Tang discloses the “estimating an available memory bandwidth based
on a fullness of a cache buffer that buffers data provided to and from a
cache,” as recited in claim 1;
2. Tang discloses “estimating the available memory bandwidth
comprises estimating the available memory bandwidth based on both
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the fullness of the cache buffer and a fullness of a memory buffer that
buffers data provided to and from the memory,” as recited in claim 9;
3. the combination of Tang and Guthrie disclose or suggest “temporarily
suspending the prefetching for a second period of time in response to
determining that the prefetch accuracy is below a third threshold,” as
recited in claim 11.
DECISION
The Examiner’s decision rejecting claims 1—7, 9—19, and 21—25 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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