Ex Parte Pouydebasque et al

Patent Trial and Appeal Board

Mar 25, 2014

12296402 (P.T.A.B. Mar. 25, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte ARNAUD POUYDEBASQUE and
ROBIN CERUTTI
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Appeal 2012-001498
Application 12/296,402
Technology Center 2800
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Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.

TIMM, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF CASE
Appellants seek review of the Examiner’s decision to reject claims 1-
13 and 20-22. We have jurisdiction under 35 U.S.C. §§ 6(b) and 134.
For the reasons articulated by the Examiner in the Answer, we
AFFIRM.

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Application 12/296,402

2
The claims are directed to a complementary metal oxide
semiconductor (CMOS) device formed on a silicon-on-insulator (SOI)
substrate including two different types of transistor structures (see, e.g, claim
1). It was known in the art to fashion such a device including a planar single
gate field effect transistor (FET) and a type of multi-gate transistor called a
FinFET (Spec. 2:22-26). Instead of a planar single gate FET, Appellants’
device includes a multi-gate FET (Spec. 3:3-7). Claim 1 is illustrative:
1. A CMOS circuit device made on a SOI substrate with
an oriented silicon surface, comprising
on a first substrate region, a multi-gate FET with an
active multi-gate FET transistor layer that contains, between
main FET-channel faces, which have the same orientation as
the silicon surface, multiple FET channel regions of a first
conductivity type, and a multi-gateFET gate stack abutting the
main FET-channel faces,
and, on a second substrate region, a FinFET with at least
one active FinFET transistor layer that contains, between
parallel main FinFET-channel faces, which have an orientation
perpendicular to that of the silicon surface, at least one FinFET
channel region of a second conductivity type opposite to the
first conductivity type, and with a FinFET gate stack abutting
the main FinFET-channel faces.
(Claims App’x at Br. 21.)
The Examiner rejects claims 1-13 and 20-22 under 35 U.S.C. § 103(a)
as obvious, relying upon Doris1 and Park2 as evidence of the obviousness of
claims 1-9 (Final Rej. 4-7; Ans. 4-7), and further applying other prior art
references in combination with Doris and Park as evidence of the
obviousness of claims 10-13 and 20-22 (Final Rej. 7-12; Ans. 7-12).

1 Doris et al., US 2004/0266076 A1, pub. Dec. 30, 2004.
2 Park, US 2005/0266645 A1, pub. Dec. 1, 2005.
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OPINION
For the reasons the Examiner states in the Answer, we affirm. We
add the following primarily for emphasis.
We begin our discussion with the rejection of claims 1-9. Claims 1-9
are rejected as obvious over the combination of Doris and Park. According
to Appellants, Doris “teaches away from the hypothetical embodiment
resulting from the proposed combination” (Br. 5). Appellants further
contend that the rejection of claims 1-9 fails to establish correspondence to
the claimed invention as a whole (Br. 7-9). For these arguments, Appellants
do not argue any claim apart from the others. We select claim 1 as
representative.
Doris teaches an integrated semiconductor circuit that includes a
planar single gate complementary metal oxide semiconductor (CMOS)
device and a double gate device, i.e., FinFET (Doris ¶ 0001). Both the
planar single gate CMOS device and FinFET device are fabricated on the
same semiconductor substrate, which can be a silicon-on-insulator (SOI)
layer (id.).
Doris discloses the following two alternatives:
In one instance, the planar single gate CMOS device is an nFET
formed on a thin silicon-on-insulator (SOI) layer and the
FinFET is a pFinFET structure having a vertical channel that
has a surface orientation at the (110) direction. Alternatively,
the planar single gate CMOS device is a pFET formed on a thin
SOI layer with a (110) surface orientation and the FinFET is an
nFinFET structure having a vertical channel that has a surface
(100) orientation.
(Id.)
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4
As properly found by the Examiner, Doris teaches the claimed
combinations of a FET with a FinFet having the orientations and
conductivities required by claim 1 (Ans. 4-5). As acknowledged by the
Examiner, the difference lies in the structure of the FET in the first region
(Ans. 5). Doris teaches using a planar single gate FET whereas the claim
requires a multi-gate FET.
There can be no real dispute that multi-gate FETs of the structure
required by claim 1 were known in the art as evidenced by Park and by
Appellants’ own Specification (see, Ans. 5; Park, generally, and Appellants’
Fig. 3 and Spec. 1-2). The benefits of multi-gate devices over single gate
devices were known in the art (Ans. 5; Park ¶¶ 0004-05; Spec. 1-2).
The Examiner’s rejection is based upon the substitution of the planar
single gate FET of Doris with a known multi-gate FET to obtain the known
advantages of the multi-gate FET (Ans. 5).
Appellants contend that Doris teaches away from the proposed
substitution because Doris teaches a single-gated device (Br. 5-6), but Doris’
silence with regard to other alternative FET structures is not a teaching
away, particularly, here, where the prior art indicates that multi-gate devices
were known in the art to have advantages over single gate-devices. In
reviewing the factual question of whether a reference teaches away one must
take care not to ignore the modifications that one skilled in the art would
make to a device borrowed from the prior art. In re ICON Health & Fitness,
Inc., 496 F.3d 1374, 1382 (Fed. Cir. 2007).
Appellants’ contentions regarding correspondence between what is
suggested by the combination of prior art and the claim as a whole (Br. 7-9;
Reply Br. 7-8) are also unpersuasive. Doris specifically teaches using a
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combination of devices with first and second conductivities and how to
integrate two devices on the same wafer so the devices have surface
orientations that enhance performance of each device (Doris ¶ 0006). “A
person of ordinary skill is also a person of ordinary creativity, not an
automaton.” KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007). When
substituting the planar single gate FET of Doris with a multi-gated FET, one
would have preserved the conductivity and orientation differences Doris
teaches as desirable while incorporating the multi-gate structure of the
known prior art. Appellants point to no convincing evidence that forming
the suggested modified device would have been outside the capabilities of
the ordinary artisan.
In the present case, using a known multi-gate FET in place of the
planar single gate FET of Doris appears to be no more than the combination
of familiar elements according to known methods that yields no more than
predictable results. Under these circumstances, the evidence supports a
conclusion of obviousness. KSR, 550 U.S. at 416.
Appellants further contend that the rejections of dependent claims 2-9
are improper (Br. 4-8; Reply Br. 4). Appellants point out that the Examiner
did not state a motivation in support of the proposed combination of
references, and further failed to establish correspondence between the
structures of the claims and the prior art (Br. 4-7). Given the response to
argument provided by the Examiner (Ans. 13-17), we do not find these
arguments convincing. A preponderance of the evidence supports the
Examiner’s finding of a reason for incorporating a multi-gate FET of the
structure of Park in place of the single gate FET of Doris. The Examiner has
pointed out where in the references the structures of the dependent claims
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are located in the proposed reference combination. Appellants’ arguments
do not adequately take into account the modifications based upon Park that
would be present in the combination in arguing that the structure of the prior
art does not correspond to the structure of the dependent claims.
The arguments directed to the further rejections of claims 10-13 and
20-22 parallel those presented against the rejection of claims 1-9. We find
those arguments unpersuasive of reversible error for the reasons stated by
the Examiner and the reasons discussed above.
In the Reply Brief, Appellants contend that the Examiner’s responses
to the arguments regarding teaching away on pages 14 and 15 of the Answer
rely upon a new ground of rejection (Reply Br. 3). The question here is
whether the Examiner abused his discretion in responding to Appellants’
arguments. However, we have no jurisdiction to review questions involving
whether an examiner abused his or her discretion. Such questions are
reviewed by way of petition to the Director under 37 C.F.R. § 1.181. In re
Berger, 279 F.3d 975, 984-85 (Fed. Cir. 2002); see also In re Hengehold,
440 F.2d 1395, 1404 (CCPA 1971).

CONCLUSION
We sustain the Examiner’s rejections.

DECISION
The Examiner’s decision is affirmed.

Appeal 2012-001498
Application 12/296,402

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TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).

AFFIRMED

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