Ex Parte Ponomarev et al

Patent Trial and Appeal Board

Jul 28, 2017

13422284 (P.T.A.B. Jul. 28, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/422,284 03/16/2012 Youri Victorovitch Ponomarev 81411731 US02 4523
65913 7590
Intellectual Property and Licensing
NXPB.V.
411 East Plumeria Drive, MS41
SAN JOSE, CA 95134
EXAMINER
KAPLAN VERBITSKY, GAIL
ART UNIT PAPER NUMBER
2855
NOTIFICATION DATE DELIVERY MODE
08/01/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip. department .u s @ nxp. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YOURI VICTOROVITCH PONOMAREV and
AXELNACKAERTS1
Appeal 2016-006241
Application 13/422,284
Technology Center 2800
Before CHUNG K. PAK, CHRISTOPHER C. KENNEDY, and
MONTE T. SQUIRE, Administrative Patent Judges.
SQUIRE, Administrative Patent Judge.
DECISION ON APPEAL2
Appellants appeal the Examiner’s decision rejecting claims 1, 2, 4—6,
10, and 11, which constitute all the claims pending in this application.
35 U.S.C. § 134(a). We have jurisdiction under 35 U.S.C. § 6(b).3
1 Appellants identify NXP B.V. as the real party in interest. App. Br. 1.
2 In our Decision, we refer to the Specification filed March 16, 2012
(“Spec.”); the Non-Final Office Action appealed from, dated October 20,
2015 (“Non-Final Act.”); the Appeal Brief dated December 7, 2015 (“App.
Br.”); the Examiner’s Answer to the Appeal Brief dated April 5, 2016
(“Ans.”); and the Reply Brief dated June 6, 2016 (“Reply Br.”).
3Although the action appealed from was a non-final rejection, we have
jurisdiction pursuant to 35 U.S.C. §§ 6 and 134 because the claims have
Appeal 2016-006241
Application 13/422,284
We AFFIRM.
The Claimed Invention
Appellants’ invention relates to a temperature sensor comprising a p-n
junction device. Spec. 1; Abstract. Claim 1 is illustrative of the claimed
subject matter on appeal and is reproduced below from the Claims Appendix
to the Appeal Brief (App. Br. 12) (key disputed claim language italicized
and bolded):
1. A temperature sensor comprising:
a p-n junction device,
a current device configured to provide a sequence of
different currents to the p-n junction device, wherein the
sequence covers an off-region, a linear region, and a saturation
region of an I-V curve for the p-n junction device,
a measurement circuit configured to measure voltage
characteristics of the p-n junction device as a function of said
sequence, and
a processor configured to determine a minimum value of
a voltage swing from said characteristics and to convert said
minimum value to a temperature value.
The References
The Examiner relies on the following prior art references* * 4 as evidence
in rejecting the claims on appeal:
Johnson US 2006/0029123 A1 Feb. 9, 2006
(hereinafter “Johnson ’123”)
Johnson US 7,083,328 B2 Aug. 1,2006
been twice presented and rejected. See Ex parte Lemoine, 46 USPQ2d 1420,
1423 (BPAI 1994).
4 The Examiner also refers to and discusses Nelson (US 4,755,741, issued
Jul. 5, 1988) as an evidentiary reference at page 2 of the Answer.
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Application 13/422,284
(hereinafter “Johnson ’328”)
D’Aquino et al., US 7,089,146 B1
(hereinafter “D ’Aquino”)
Jain et al, US 2006/0221741 Al
(hereinafter “Jain ’741”)
Jain et al, US 7,260,007 B2
(hereinafter “Jain ’007”)
Aug. 8, 2006
Oct. 5, 2006
Aug. 21,2007
Mamoru Terauchi, Temperature Dependence of the Subthreshold
Characteristics of Dynamic Threshold Metal—Oxide—Semiconductor Field-
Effect Transistors and Its Application to an Absolute-Temperature Sensing
Scheme for Low-Voltage Operation, 46(7 A) Japanese Journal of Applied
Physics, 4102—04 (2007) (hereinafter “Terauchi”).
The Rejections
On appeal, the Examiner maintains the following rejections:
1. Claims 1, 4—6, and 10 are rejected under pre-AIA
35 U.S.C. § 103(a) as being unpatentable over Jain5 in view of Terauchi
(“Rejection 1”). Non-Final Act. 3; Ans. 2.
2. Claim 2 is rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Jain and Terauchi, as applied to claims 1, 4—6, and 10
above, and further in view of Johnson6 (“Rejection 2”). Non-Final Act. 6;
Ans. 2.
3. Claim 11 is rejected under 35 U.S.C. § 103(a) as being
unpatentable over Jain and Terauchi, as applied to claims 1, 4—6, and 10
5 The Examiner refers to Jain ’741 and Jain ’007 collectively as “Jain.”
Non-Final Act. 3.
6 The Examiner refers to Johnson ’123 and Johnson ’328 collectively as
“Johnson.” Non-Final Act. 6.
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Application 13/422,284
above, and further in view of D’Aquino (“Rejection 3”). Non-Final Act. 7;
Ans. 2.
OPINION
Having considered the respective positions advanced by the Examiner
and Appellants in light of this appeal record, we affirm the Examiner’s
rejections for the reasons set forth in the Answer to the Appeal Brief and
Non-Final Office Action, which we adopt as our own. We highlight and
address specific findings and arguments below for emphasis.
Rejection 1
Claims 1 and 10. Appellants argue independent claims 1 and 10 as a
group. We select claim 1 as representative of this group and claim 10 stands
or falls with claim 1. 37 C.F.R. § 41.37(c)(l)(iv).
The Examiner determines that the combination of Jain and Terauchi
suggests a temperature sensor satisfying all of the limitations of claim 1 and
would have rendered claim 1 obvious. Non-Final Act. 3—6.
The Examiner finds that Jain teaches or suggests the majority of the
limitations of claim 1, but that Jain is silent as to whether the diode junction
is a “p-n junction,” as recited in the claim. Non-Final Act. 3—5 (citing Jain,
Figs. 1, 3; 130). The Examiner, however, relies on Terauchi for suggesting
this missing limitation. Id. at 5.
In particular, the Examiner finds that Jain and Terauchi are in the art
of using temperature-dependent elements, i.e., diodes, bipolar transistors,
transducers, and DTMOS transistors, in order to derive temperature values,
e.g., temperature values proportional to absolute temperature from known or
measured currents and/or voltages and that Terauchi teaches a transducer
that is a DTMOS transistor for sensing absolute temperatures from minimum
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voltage swing values. Non-Final Act. 5 (citing Terauchi, Fig. 1, pp. 4102—
04).
Based on the above findings, the Examiner concludes that
It would have been obvious for one of ordinary skill in the art at
the time of the invention to replace the diode/junction of Jain
with the DTMOS transistor ... as taught by Terauchi, because
the DTMOS of Terauchi also has temperature dependent
characteristics, indicative of temperature, thus, because two of
them are alternate type of temperature sensing
devices/transducers, which would perform the same function of
sensing temperature of a range of current/ voltage characteristics,
if one is replaced with another.
Non-Final Act. 5—6.
Appellants argue that the Examiner’s rejection of claim 1 should be
reversed because Jain does not teach or suggest the limitation “wherein the
sequence covers an off region, a linear region, and a saturation region of an
I-V curve for the p-n junction device,” as required by the claim. App. Br. 5—
6; Reply Br. 2-4. Appellants further argue that Jain teaches away from
using the three recited regions and Terauchi and the other cited references
fail to remedy the deficiencies of Jain. App. Br. 6; Reply Br. 2.
Appellants’ arguments are not persuasive of reversible error in the
Examiner’s rejection. On the record before us, the preponderance of the
evidence and sound technical reasoning support the Examiner’s analysis and
determination that the combination of Jain and Terauchi suggests all of the
limitations of claim 1, including “wherein the sequence covers an off region,
a linear region, and a saturation region of an I-V curve for the p-n junction
device,” and would have rendered the claim obvious. Jain, Figs. 1, 3; 130;
Terauchi, Fig. 1, pp. 4102—04.
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As the Examiner finds (Ans. 2), although Jani does not explicitly
teach a sequence of different currents to cover a cut off region, a saturation
region and a linear region, Jain does teach a transistor and I-V curve that is
applied with two or more different current levels spaced apart to calibrate
the sensor, which corresponds to the “sequence of different currents”
element of claim 1. Jain 130, Fig. 3. In particular, paragraph 30 of Jain
states:
To obtain a more accurate voltage reading, two or more
different current levels II, 12 may be applied to one or more of
the thermal diodes. The different current levels may be injected
into a diode one at a time and spaced apart by an interval of a
few nanoseconds and two or more corresponding different
voltages VI, V2 may be captured and sampled in the ADC. The
different currents provide two or more additional data points for
the temperature reading. The readings can be applied to a
current/voltage curve specific to a particular diode temperature,
such as the curves shown in FIG. 3. The curves may be used to
eliminate calibration errors. The data points can be averaged to
eliminate spurious spikes in voltage readings that may result in
false alarms. The number of data points can be increased to
increase accuracy further.
As the Examiner further finds (Ans. 3), Jain teaches that the different
current levels provide additional data points and that increasing the number
of data points increases the accuracy of the device’s temperature reading.
Jain 130.
Moreover, as the Examiner finds (Ans. 2) and evidenced by Nelson,
the “off-region, a linear region, and a saturation region of an I-V curve for
the p-n junction device” were known in the art. See Nelson, Fig. 1, cols. 3—
4. In particular, columns 3^4 of Nelson describe and Figure 1 of Nelson
depicts the output characteristics of a typical bipolar transistor p-n junction
for different sequence values of the base currents including: (1) the cut-off
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region (represented by the shaded area 101 between line 100 and the
ordinate in Fig. 1); (2) the saturation region (represented by line 112 in Fig.
1); and (3) the linear/active region (represented by the shaded area
associated with lines 100-110 in Fig. 1).
The Examiner’s explanation for why one of ordinary skill would have
provided a sequence of different currents along a given I-V curve of Jain
covering all three regions is also supported by a preponderance of the
evidence and articulated reasoning with rational underpinning. See In re
Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) (requiring “some articulated
reasoning with some rational underpinning to support the legal conclusion of
obviousness”).
In particular, as the Examiner explains (Ans. 3), because Jain teaches
that providing additional data points along the I-V curve increases accuracy
(Jain 130, Fig. 3), one of ordinary skill in the art would have had reason to
provide a sequence of currents covering all three regions in order to improve
accuracy and reduce calibration errors.
Appellants fail to direct us to sufficient evidence or provide an
adequate technical explanation to establish why the Examiner’s articulated
reasoning lacks a rational underpinning or is otherwise based on some other
reversible error.
We do not find Appellants’ argument that Jain teaches away from
using the three recited regions (App. Br. 6) persuasive of reversible error
because Appellants do not identify sufficient evidence to support it, and we
will not read into the reference a teaching away where no such language
exists. Cf. DyStar Textilfarben GmbHv. C.H. Patrick Co., 464 F.3d 1356,
1364 (Fed. Cir. 2006); see also In re Fulton, 391 F.3d 1195, 1201 (finding
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that there is no teaching away where the prior art’s disclosure “does not
criticize, discredit, or otherwise discourage the solution claimed”). Indeed,
as the Examiner correctly points out (Ans. 4), Appellants do not identify or
direct us to any teaching—whether in Jain or elsewhere in the record—that
criticizes, discredits, or discourages the use of temperature sensing in a
sequence covering an off region, a linear region, and a saturation region, as
claimed.
Appellants’ assertion that “Terauchi and the other references of record
fail to remedy the deficiencies of Jain” (App. Br. 6) is not persuasive
because it is conclusory and a naked assertion that the prior art fails to teach
or suggest a claim’s limitations is not an argument in support of separate
patentability. Cf. In reLovin, 652 F.3d 1349, 1356—57 (Fed. Cir. 2011);
37C.F.R. §41.37(c)(l)(iv).
Claim 4. Claim 4 depends from claim 1 and further recites “wherein
said sequence covers a range of currents such that the voltage characteristics
comprise a full sweep of the current-voltage behavior of the p-n junction
device.” App. Br. 12 (Claims App.).
Appellants argue that the Examiner’s rejection of claim 4 should be
reversed for principally the same reasons previously presented above in
response to the Examiner’s rejection of claim 1. App. Br. 7. In particular,
Appellants argue claim 4 is allowable due to its dependency from claim 1
and because Jain fails to disclose a sequence of currents that covers an off
region, a linear region, and a saturation region, it cannot provide a “full
sweep of the current-voltage behavior of the p-n junction device,” as
claimed. Id. at 7. Appellants also contend that the Examiner “presents a
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conclusory statement (‘cover[s] a full sweep’) without explanation.” Id. at
7.
We do not find Appellants’ arguments persuasive of reversible error
for the well-stated reasons provided by the Examiner at pages 4 and 5 of the
Answer and for essentially the same reasons discussed above regarding the
patentability of claim 1. In particular, we concur with the Examiner findings
(Ans. 4) that the “full sweep” would only be generated in response to the
sequence of the currents which covers the all three regions and that one of
ordinary skill would have had reason to provide a sequence of currents
covering all three regions in order to improve accuracy and reduce
calibration errors, as suggested by Jain. See Jain 130, Fig. 3; see also
Nelson, Fig. 1, cols. 3^4.
Claims 5 and 6. Appellants argue claims 5 and 6 as a group. App. Br.
8. Appellants, however, do not present any additional substantive arguments
in support of the patentability of these claims. Rather, Appellants merely
assert that “claims 5 and 6 are allowable at least due to their dependencies
from an allowable base claim.” App. Br. 8.
We do not find this argument persuasive for the same reasons
discussed above regarding the patentability of claims 1.
Accordingly, we affirm the Examiner’s rejection of claims 1, 4—6, and
10 under 35 U.S.C. § 103(a) as obvious over the combination of Jain and
Terauchi.
Rejections 2 and 3
Appellants do not present any additional substantive arguments in
response to the Examiner’s Rejections 2 and 3, stated above.
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Rather, Appellants rely on the same arguments presented above in
response to the Examiner’s Rejection 1 regarding the combination of Jain
and Terauchi. See App. Br. 9 (asserting that “Johnson fails to remedy the
deficiencies of Jain in view of Terauchi for claim 1” and “is allowable at
least due to its dependency from an allowable base claim”); App. Br. 10
(asserting that “D’Aquino fails to remedy the deficiencies of Jain in view of
Terauchi for claim 10” and “is allowable [at least] due to its dependency
from an allowable base claim”).
We do not find these arguments persuasive for the same reasons
discussed above for affirming Rejection 1 and, accordingly, affirm the
Examiner’s Rejections 2 and 3.
DECISION/ORDER
The Examiner’s rejections of claims 1, 2, 4—6, 10, and 11 are
affirmed.
It is ordered that the Examiner’s decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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