Ex Parte Perez et al

Board of Patent Appeals and Interferences

Jun 1, 2009

11081918 (B.P.A.I. Jun. 1, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte RAUL A. PEREZ and MOHAMMAD ALI AL-SHYOUKH
____________

Appeal 2009-001600
Application 11/081,918
Technology Center 2800
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Decided:1 June 1, 2009
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Before ROBERT E. NAPPI, CARLA M. KRIVAK,
and THOMAS S. HAHN, Administrative Patent Judges.

KRIVAK, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1, 6-12, and 16-20. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).

Appeal 2009-001600
Application 11/081,918

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STATEMENT OF CASE
Appellants’ claimed invention is a power efficient, dynamically
biased buffer for low voltage regulators (Spec. ¶ [0001]).
Independent claim 1, reproduced below, is representative of the
subject matter on appeal.
1. A buffer circuit comprising:

a first transistor having a first end coupled to an output node
and a control node coupled to an input node;

a second transistor coupled to a second end of the first
transistor;

a first sense device coupled to the output node;

a first current source coupled to the output node;

a bipolar device coupled to the output node and having a
control node coupled to the second end of the first transistor;

a third transistor having a control node coupled to a control
node of the second transistor;

a second sense device coupled to the third transistor; and

a second current source coupled to the third transistor.

REFERENCE
Murabayashi US 5,001,365 Mar. 19, 1991
The Examiner rejected claims 1, 6-12, and 16-20 under 35 U.S.C.
§ 102(b) based upon the teachings of Murabayashi.
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Application 11/081,918

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Appellants contend that the transistor 1151 in Murabayashi does not
correspond to the claimed second current source coupled to a third transistor
as it is not a current source, is not coupled to transistor 103, and does not
supply current to transistor 103 (App. Br. 4).2

ISSUE
Did Appellants establish that transistor 1151 of Murabayashi does not
correspond to the second current source recited in claims 1 and 12?

FINDINGS OF FACT
1. Appellants’ invention includes a second current source (I1; Fig.
3) coupled to a third transistor (MN1; Fig. 3).
2. Murabayashi teaches a third transistor 103 (Fig. 14A). The
source-drain current path of NMOS 113 is connected in parallel with the
source drain current path of the PMOS 103 and a CMOS inverter 151 (Fig.
14B). The inverter includes PMOS 1511 and NMOS 1512 and has its input
terminal connected with an output terminal 242 of CMOS inverter (col. 16,
ll. 36-43).

PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citing Minn. Mining & Mfg.

2 The Amended Appeal Brief filed October 29, 2007, is referred to
throughout this opinion.
Appeal 2009-001600
Application 11/081,918

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Co. v. Johnson & Johnson Orthopaedics, Inc., 976 F.2d 1559, 1565 (Fed.
Cir. 1992)). See also In re Paulsen, 30 F.3d 1475, 1478-79 (Fed. Cir. 1994).
“Anticipation of a patent claim requires a finding that the claim at issue
‘reads on’ a prior art reference.” Atlas Powder Co. v. IRECO, Inc., 190 F.3d
1342, 1346 (Fed. Cir. 1999) (quoting Titanium Metals Corp. of Am. v.
Banner, 778 F.2d 775, 781 (Fed. Cir. 1985)).

ANALYSIS
The Examiner rejected claims 1, 6-12, and 16-20 as anticipated by
Murabayashi, finding that Murabayashi teaches all the elements of
independent claims 1 and 12. Appellants argue this rejection with respect to
independent claims 1 and 12, claims 6-11 and 16-20 standing or falling
therewith (App. Br. 4).
On pages 3 and 4 of the Answer, the Examiner identifies how each
element of claim 1 is taught in figures 14A and 14B of Murabayashi. The
Examiner finds that transistor 1511 meets the claimed second current source
(FF 2). Appellants contend that contrary to the Examiner’s findings, the
transistor 1511 in Murabayashi is not a current source as claimed nor is it
coupled to transistor 103 (which the Examiner equates to the third
transistor). Additionally, Appellants contend that transistor 1511 does not
supply current to transistor 103. (App. Br. 4) However, as found by the
Examiner (Ans. 6) and shown in Figures 14A and 14B of Murabayashi, the
gate of transistor 1511 is indeed coupled to the gate of transistor 103.
Further, the claims do not require that the second current source supply
current to the third transistor. Additionally, Appellants have identified no
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evidence nor presented arguments to support the contention that transistor
1511 is not a current source.
Thus, the Examiner has shown that Murabayashi teaches the disputed
elements of claims 1 and 12. Accordingly, Murabayashi anticipates claims
1, 6-12, and 16-20.

CONCLUSION
Appellants have not established that the Examiner erred in finding that
transistor 1151 of Murabayashi corresponds to the second current source in
rejecting claims 1, 6-12, and 16-20 under 35 U.S.C. § 102.

DECISION
The Examiner’s decision rejecting claims 1, 6-12, and 16-20 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

KIS

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