Ex Parte Pendse et al

Patent Trial and Appeal Board

Dec 19, 2014

10960893 (P.T.A.B. Dec. 19, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte RAJENDRA PENDSE and SAMUEL TAM
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Appeal 2012-012616
Application 10/960,8931
Technology Center 2800
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Before JEFFREY T. SMITH, N. WHITNEY WILSON, and
KIMBERLY J. McGRAW, Administrative Patent Judges

McGRAW, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the rejection of:
1. Claims 18, 19, 21, 38, and 40 under 35 U.S.C. § 103(a) as being
unpatentable over Takeshita et al. (6,376,917 B1, Apr. 23, 2002)
(“Takeshita”) in view of Lebby et al. (5,818,404, Oct. 6, 1998)
(“Lebby”), and further in view of Miller et al. (5,426,405, June 20,
1995) (“Miller”). Ans. 5.
2. Claims 43–53 under 35 U.S.C. § 103(a) as being unpatentable over
Takeshita in view of Lebby. Ans. 11.

1 According to Appellants, the real party in interest is Stats ChipPAC, LTD.,
of Singapore. App. Br 1.
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3. Claim 23 under 35 U.S.C. § 103(a) as being unpatentable over
Takeshita in view of Lebby, and further in view of Miller and
Inaba et al. (6,166,443, Dec. 26, 2000) (“Inaba”). Ans. 19.
We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
BACKGROUND
Appellants’ invention is directed to chip scale semiconductor device
packaging and methods of making such packaging. Spec. ¶ 2; App. Br 14–
18 (Claim App’x). Claims 18, 38, 43, 49 are independent.
Product-by-process claims 18 and method claim 43 are representative
and are reproduced below:

18. A semiconductor package, comprising:
a substrate having conductive traces on first and second
surfaces, the conductive traces being constructed as coplanar
waveguides;
a first semiconductor die mounted on a central region of
the first surface of the substrate and electrically connected to
the conductive traces on the first surface of the substrate with a
plurality of first bumps, the first bumps being mechanically and
electrically connected to the conductive traces on the first
surface of the substrate using a solid state interconnect in
which the first bumps have been deformed against pads on the
conductive traces without melting either mating surface, the
first semiconductor die having a height above the first surface
of the substrate;
a plurality of second bumps formed on the first surface of
the substrate around a periphery of the first semiconductor die,
the second bumps being electrically connected to the first
semiconductor die through the conductive traces on the first
surface of the substrate, the second bumps having a height
greater than the height of the first semiconductor die;
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and a second semiconductor die mounted on a central
region of the second surface of the substrate and electrically
connected to the conductive traces on the second surface of the
substrate with a plurality of third bumps, the third bumps being
mechanically and electrically connected to the conductive
traces on the second surface of the substrate using a solid state
interconnect in which the third bumps have been deformed
against pads on the conductive traces without melting either
mating surface, the solid state interconnect achieving about
0.1 mm pitch between the first and third bumps.

43. A method of making a semiconductor package,
comprising:
providing a substrate having conductive traces on first
and second surfaces;
mounting a first semiconductor die on a central region of
the first surface of the substrate and electrically connected to
the conductive traces on the first surface of the substrate with a
plurality of first bumps, the first bumps being mechanically and
electrically connected to the conductive traces on the first
surface of the substrate using a solid state interconnect made
by application of heat and mechanical force to deform the first
bumps against pads on the conductive traces without melting
either mating surface, the first semiconductor die having a
height above the first surface of the substrate;
forming a plurality of second bumps on the first surface
of the substrate around a periphery of the first semiconductor
die, the second bumps being electrically connected to the first
semiconductor die through the conductive traces on the first
surface of the substrate, the second bumps having a height
greater than the height of the first semiconductor die; and
mounting a second semiconductor die on a central region
of the second surface of the substrate and electrically connected
to the conductive traces on the second surface of the substrate
with a plurality of third bumps.
App. Br 51–52, 54–55 (Claim App’x) (limitations at issue italicized).
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ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments the Examiner erred. App. Br. 10–50. We are unpersuaded by
Appellants’ contentions.
The Examiner found Takeshita describes a method of making a
semiconductor package that is the different from the claimed invention
because Takeshita fails to show that the bumps were mechanically and
electrically connected to the conductive traces on the first surface of the
substrate using a solid state interconnect made by application of heat and
mechanical force to deform the first bumps against pads on the conductive
traces without melting either mating surface. See e.g., Ans. 5–6, 8–9, 11–13.
The Examiner found Lebby describes an integrated electro-optical package
wherein solder balls were subject to a thermo-compression bonded process
to mechanically and electrically connect conductive traces. See e.g., Ans. 6,
9, 12, 13; Lebby col. 9, ll.1-21. The Examiner found the thermo-
compression bonding process comprises deforming the solder balls against
the pads when the conductive traces without melting either mating surface.
See e.g., id. The Examiner found that the thermo-compression bonding
process inherently comprises mechanically and electrically connecting
bumps to the conductive traces on the first surface of the substrate wherein
the bumps have been deformed against pads on the conductive traces
without melting either mating surface. See e.g., id.
The Examiner also found that one of ordinary skill in the art would
understand that a thermo-compression bonding process involving gold
bumps on a chip or substrate would utilize a bonding temperature of 300ºC
for gold bonding that would soften (i.e., not melt) the gold material and
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increase the diffusion bonding process. Ans. 23; see also Ans. 23–24
(stating that it is well known in the art that a thermo-compression bonding
process involves a temperature of 300ºC and pressure of up to 1N for an 80
μm diameter bump).
The Examiner concluded it would have been obvious to one of
ordinary skill in the art to perform Takeshita’s method of making a
semiconductor package utilizing a thermo-compression bonded process such
as described by Lebby. See e.g., Ans. 6, 9, 12.
Appellants’ primary argument is that the Examiner erred in
concluding independent claims 18, 38, 43, and 49 would have been obvious
over the cited art because the art does not teach “first bumps being
mechanically and electrically connected to the conductive traces on the first
surface of the substrate using a solid state interconnect in which the first
bumps have been deformed against pad on the conductive traces without
melting either mating surface” as recited in independent claim 18 and
similarly recited in independent claims 38, 43, and 49.2 See e.g., App. Br.
39. Appellants argue that Lebby does not explicitly show that the bumps are
mounted to pads without melting. Appellants further argue that the
Examiner’s reasoning that the limitation is inherent is in error because “the
Lebby reference explicitly describes the thermo-compression bonding

2 Appellants make similar arguments regarding limitations found in
independent claims 18 and 38 directed to third bumps being mechanically
and electrically connected to the conductive traces on the second surface of
the substrate using a solid state interconnect in which the third bumps have
been deformed against pads on the conductive traces without melting either
mating surface. The reasoning applied to the limitations involving the first
bumps also applies to the limitations involving the third bumps.
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process by explaining that the bump material is melted to form the
mechanical connection.” See e.g., App. Br. 16, citing Lebby col. 8:52-56.
Appellants have not directed us to evidence that establishes thermo-
compression bonding process of Lebby occurs under conditions that
necessarily cause melting of the mating surfaces. Lebby does not describe
such a thermo-compression bonding processes in the portion of the reference
cited by Appellants. The description appearing in column 8 describes the
types of materials and their characteristics that are suitable for use as bumps.
Appellants have not directed us to evidence that distinguished the materials
and process conditions utilized in the cited prior art processes from the
materials and conditions required by the claimed invention. Appellants have
not directed us to evidence that establishes a person of ordinary skill in the
art would have understood that thermo-compression bonding process could
occur under conditions that necessarily cause melting of the mating surfaces
and Lebby describes these conditions.
Moreover, the Appellants fail to address the Examiner’s findings that
one of ordinary skill in the art would understand that a thermo-compression
bonding process involving gold bumps on a chip or substrate would soften
(i.e., not melt) the gold material and increase the diffusion bonding process.
Ans. 23. As such, Appellants’ arguments fail to persuasively rebut the
Examiner’s finding that one of skill in the art would understand that Lebby
teaches using a thermo-compression bonding process and that it was well
known to one of skill in the art that in a thermo-compression bonding
process results in a solid state interconnect through softening (i.e., not
melting). Ans. 23–24.
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Accordingly, we are not persuaded the Examiner reversibly erred in
concluding that independent claims 18, 38, 43, and 49 would have been
obvious over the cited art.
Appellants next argue that the Examiner erred in concluding that one
of skill in the art would have found it obvious to modify solid state
interconnects of Takeshita to provide the particular solid state interconnects
as taught by Lebby “for the purposes of transferring heat energy from a
semiconductor device.” See e.g., App. Br. 19. Appellants contend that this
rationale is insufficient as transferring heat energy is not discussed or
supported by either the Takeshita or Lebby references. Id.
This argument is not persuasive. The Supreme Court has held that in
analyzing the obviousness of combining elements, a court need not find
specific teachings, but rather may consider “the background knowledge
possessed by a person having ordinary skill in the art” and “the inferences
and creative steps that a person of ordinary skill in the art would employ.”
See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). Here, the
Examiner found, and we agree, that one of ordinary skill in the art would
understand that the solid state interconnects of Lebby would transfer heat
energy from a semiconductor device.
Appellants have not provided sufficient argument or evidence to rebut
the Examiner’s finding. Indeed, Appellants appear to concede that Lebby’s
solid state interconnects are effective at transferring heat as Appellants also
argue that the Examiner has not provided evidence that Lebby’s
interconnects are more effective at transferring heat than the reflowed solder
balls of the Takeshita reference. App. Br. 19 (emphasis added). However,
superior results are not required. It is sufficient that the Examiner found that
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it was well known that solder joining and thermo-compression bonding are
interchangeable methods to form a solid state interconnect. See e.g., Ans.
22. As such, Appellants’ argument is not persuasive of Examiner error.
Appellants argue that the Examiner has not provided an adequate
rationale for modifying Takeshita to include coplanar waveguides as taught
by Miller and recited in independent claims 18 and 38. App. Br 20.
We disagree. The Examiner found that Miller teaches conductive
traces connected as coplanar waveguides connected to a micro-strip
transmission line “for the purposes of transmitting a signal along a
conductive path on the substrate.” Office Act. 11–12. The Examiner further
found that it is “well known in the art that conductive traces can be
constructed as coplanar waveguides” and that “coplanar waveguides and/or
microstrip lines are interchangeable.” Office Act. 14.
Appellants have provided no persuasive argument that the Examiner’s
findings are in error. As such, we find that the use of coplanar waveguides
for the purpose of transmitting a signal along a conductive path on a
substrate is an objective and reasonable rationale reason to modify
Takeshita.
Appellants also make a “teaching away” argument, asserting that
because Lebby teaches bumps that can be partially melted, Lebby teaches
away from forming a connection without melting either mating surface. See
e.g., App. Br 18. Similarly, Appellants argue that because Miller teaches a
clamping structure that has advantages over a solder connection, that Miller
also teaches away from using a solid state interconnect in which the first
bumps have been deformed against pads on the conductive traces without
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melting either mating surface in favor of a clamping structure. See e.g.,
App. Br 22–24.
These arguments are not persuasive. A prior art’s mere disclosure of
more than one alternative does not constitute a teaching away from any of
these alternatives “because such disclosure does not criticize, discredit, or
otherwise discourage the solution claimed….” In re Fulton, 391 F.3d 1195,
1201 (Fed. Cir. 2004). Appellants have not pointed to any teaching in
Lebby or Miller that criticizes, discredits, or otherwise discourages the
solution claimed.
Appellants argue that the Examiner erred in rejecting claim 18
because the cited art does not teach or suggest a “solid state interconnect
achieving about 0.1 mm pitch between the first and third bumps” as recited
in the claim. App. Br 24. Appellants assert that Takeshita teaches a
structure with a larger 0.3 mm pitch and that Lebby and Miller do not cure
this deficiency. Id.
This argument is not persuasive as Appellants fail to address the
Examiner’s finding that Lebby teaches a solid state interconnect achieving
about 0.1 mm pitch between the first and third bump. Ans. 6, citing Lebby
8:22–67 (teaching an interconnect of 0.08mm). The Examiner found that the
“solid state interconnect achieving about 0.1 [mm] pitch between the first
and third bump” would have been obvious since the final structure is the
same. Ans. 6. The Examiner further noted that Appellants have not asserted
that the recited dimensions are critical or that claimed dimension provides
any unexpected results. Id. Appellants have provided no persuasive
argument as to why the Examiner’s findings or reasoning are in error.
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Appellants’ remaining arguments have been fully considered but are
not deemed persuasive.
For the above reasons, Examiner’s decision rejecting independent
claims 18, 38, 43, and 49, and dependent claims 19, 21, 23, 40, and 44–48,
50–53, which have not been argued separately, is sustained.
DECISION
The Examiner’s decision rejecting claims 18, 19, 21, 23, 38, 40, and
43–53 as unpatentable under 35 U.S.C. § 103(a) is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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