Ex Parte Patapoutian et al

Patent Trial and Appeal Board

Jun 2, 2016

13170802 (P.T.A.B. Jun. 2, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/170,802
98068 7590
Hollingsworth Davis
8000 West 78th Street
Suite 450
06/28/2011
06/06/2016
Minneapolis, MN 55439
FIRST NAMED INVENTOR
Ara Patapoutian
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
STX.051.Al 4464
EXAMINER
BEJCEK II, ROBERT H
ART UNIT PAPER NUMBER
2129
NOTIFICATION DATE DELIVERY MODE
06/06/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
tdotter@hdpatlaw.com
roswood@hdpatlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Exparte ARA PATAPOUTIAN andARVIND SRIDHARAN
Appeal2014-007605
Application 13/170,802
Technology Center 2100
Before CAROLYN D. THOMAS, JEFFREYS. SMITH, and
TERRENCE W. MCMILLIN, Administrative Patent Judges.
SMITH, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2014-007605
Application 13/170,802
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner's Final
Rejection of claims 1--4, 6-14, and 16-20, which are all the claims pending
in the application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Representative Claims
1. A method of accessing a memory device having multiple
memory units, comprising:
storing a training dataset in a memory unit after the
memory unit has experienced a predetermined number of
program/erase cycles, the training dataset comprising at least
one of a known data pattern and at least one codeword capable
of being decoded in a training dataset field of each memory unit
of a memory device;
determining one or more reference voltages using the
training dataset field of the memory unit; and
using the reference voltages to read other fields of the
memory unit.
11. A method of accessing a memory device having multiple
memory units, comprising:
storing codewords in a memory unit of a memory device,
the codewords including a least one codeword that has a code
rate dependent on a number of program/erase cycles
experienced by the memory unit;
successfully decoding the at least one codeword;
determining a reference voltage for the memory unit
using the successfully decoded codeword; and
using the reference voltage to read other codewords of
the memory unit.
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Appeal2014-007605
Application 13/170,802
Strasser
Yang
Prior Art
US 2011/0182119 Al
US 2011/0022886 Al
Examiner's Rejections
July 28, 2011
Jan.27,2011
Claims 11and12 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Strasser. Final Act. 7.
Claims 1--4, 6-10, 13, 14, and 16-20 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Strasser and Yang. Final Act. 8.
ANALYSIS
We adopt the findings of fact made by the Examiner in the Final
Rejection and Examiner's Answer as our own. We concur with the
conclusions reached by the Examiner for the reasons given in the
Examiner's Answer. We highlight the following for emphasis.
Section 102 rejection of claim 11
Claim 11 recites storing "codewords including a least one codeword
that has a code rate dependent on a number of program/erase cycles
experienced by the memory unit." Paragraph 107 of Strasser discloses
selecting different error-correcting code (ECC) algorithms to achieve
different metrics, such as performance, efficiency, and robustness metrics.
Paragraph 108 of Strasser discloses selecting a more robust ECC algorithm
to extend the life of solid-state media written 100,000 times.
Appellants contend Strasser does not disclose changing the ECC
algorithm during the life cycle of the device, in response to the storage
medium experiencing PIE cycles. App. Br. 6; Reply Br. 6-7. We highlight
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Appeal2014-007605
Application 13/170,802
claim 11 does not recite changing the codeword during the lifecycle of the
device, in response to anything. Appellants' contention that Strasser does
not disclose changing the ECC algorithm during the life cycle of the device
in response to the storage medium experiencing PIE cycles, is not
commensurate with the scope of the claim.
Appellants' Specification discloses the code rate of a codeword is
related to the amount of redundant data, or parity bits, added to the
codeword. An encoder that adds more parity bits to the codeword lowers the
code rate and increases the likelihood of correcting errors. See Spec. 6: 1-12.
Paragraphs 107 and 108 of Strasser disclose an encoder that extends the
usage limit of solid-state storage media written 100,000 times using a robust
ECC algorithm. We find the meaning of "robust" that describes the robust
ECC algorithm of Strasser means that the algorithm lowers the code rate by
adding more parity bits to the codeword. Appellants have not persuasively
explained why the claimed "at least one codeword that has a code rate
dependent on a number of program/erase cycles experienced by the memory
unit" is any different than the codeword generated from the robust ECC
algorithm which extends the life of a memory written 100,000 times as
disclosed by Strasser.
We sustain the rejection of claim 11 under 35 U.S.C. § 102.
Section 102 rejection of claim 12
Appellants contend that Strasser does not disclose "the code rate of
the at least one codeword decreases with increasing program/erase cycles
experienced by the memory unit" as recited in claim 12. Reply Br. 7.
Appellants' contention is based on the premise that paragraph 107 of
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Appeal2014-007605
Application 13/170,802
Strasser describes not dynamically modifying the ECC algorithm. Reply Br.
5. However, the sentence from paragraph 107 of Strasser cited by
Appellants simply discloses that "[i]n one embodiment, ECC algorithms are
not dynamically modified." This sentence does not mean that in every
embodiment, the ECC algorithms are not dynamically modified. Rather, we
find this sentence means that in one embodiment, the ECC algorithms are not
dynamically modified, while in other embodiments, they are. This meaning
is consistent with the rest of the paragraph, which discloses selecting
different ECC algorithms to achieve different metrics. This meaning is also
consistent with the following paragraph, which discloses selecting a robust
ECC algorithm to extend the life of a memory that has been written 100,000
times. Thus, Appellants have not persuasively explained why disclosing that
one embodiment does not dynamically modify ECC algorithms means that
every embodiment does not dynamically modify ECC algorithms.
The Examiner finds Strasser discloses a more robust rate is needed
after more PIE cycles are experienced, which indicates a smaller code rate.
Ans. 7. The Examiner's finding is supported by paragraph 107 of Strasser,
which discloses selecting different ECC algorithms to achieve different
metrics, such as performance, efficiency, and robustness metrics, and
paragraph 108, which discloses selecting a more robust ECC algorithm to
extend the life of solid-state media written 100,000 times. We agree with
the Examiner that selecting a more robust ECC algorithm to extend the life
of solid-state media written 100,000 times describes "the code rate of the at
least one codeword decreases with increasing program/erase cycles
experienced by the memory unit" within the meaning of claim 12.
We sustain the rejection of claim 12 under 35 U.S.C. § 102.
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Appeal2014-007605
Application 13/170,802
Section 103 rejection of claims 1 and 13
Appellants contend Strasser does not teach "storing a training dataset
in a memory unit after the memory unit has experienced a predetermined
number of program/ erase cycles" as recited in claim 1, because Strasser does
not teach taking actions after a memory unit has experienced a
predetermined number of program/erase cycles. App. Br. 7-8. We find
Appellants' contention unpersuasive for the reasons given in our analysis of
claims 11 and 12.
Appellants further argue "[ m ]odifying Strasser to store a training
sequence when the data is written, as taught by Yang, would undermine the
alleged suggestion of later storage," and "improperly undermine the alleged
suggestions of Strasser." App. Br. 9. Appellants appear to be arguing that
Yang teaches away from Strasser.
We note a reference does not teach away if it merely expresses a
general preference for an alternative invention but does not "criticize,
discredit, or otherwise discourage" investigation into the invention claimed.
In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004). Strasser does not recite
its intended purpose as being specifically to provide for later storage; rather,
Strasser is directed towards determining read voltage thresholds for storage
media, and Yang is directed towards providing data read methods. See
Strasser, Abstract; see also Yang, Abstract. We agree with the Examiner's
findings that Yang's "training sequence could be stored with the data under
the framework of Strasser." Ans. 10-11.
Accordingly, we sustain the rejection of claim 1under35 U.S.C.
§ 103. Appellants present arguments for the patentability of claim 13 similar
to those presented for claim 1 which we find unpersuasive.
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Appeal2014-007605
Application 13/170,802
Section 103 rejection of claim 8
Claim 8 recites "the codeword that is capable of being decoded has a
code rate that is lower than other codewords of the memory unit."
Appellants argue Strasser's "one or more ECC codes (asserted as
corresponding to the claimed codewords)" do not teach or suggest "that
multiple ECC algorithms ... are used for the ECC codes and that one ECC
algorithm would be more robust than other ECC algorithms of the same
memory unit." App. Br. 10. We agree with the Examiner's findings that
Strasser's "more robust code rate" is "needed for more PIE cycles
experienced, which indicates a smaller code rate," and Strasser's "use of an
encoder to generate multiple error-correcting codes (ECC)" for "correcting a
single-bit or double-bit errors," represents "multiple code words with
variable code rates wherein the one capable of being decoded has the lower
code rate." Ans. 7, 11; see Strasser i-fi-f 107-108, 152.
Appellants contend Strasser does not imply the same encoder uses
multiple error-correcting codes. Reply Br. 8. We highlight paragraph 107
of Strasser discloses in one embodiment, ECC algorithms are not
dynamically modified, which implies in other embodiments, they are.
Further, paragraph 107 discloses selecting an algorithm to achieve one or
more metrics. Paragraph 108 teaches selecting a robust algorithm for an
older memory to achieve the metric of extending the useful life of the
memory, which implies selecting a different algorithm to achieve a different
metric when the memory is newer.
Accordingly, we sustain the rejection of claim 8 under 35 U.S.C.
§ 103.
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Appeal2014-007605
Application 13/170,802
Section 103 rejection of claims 9 and 17
Claim 9 recites "the code rate of the codeword that is capable of being
decoded is a function of a likelihood that data stored in the memory unit will
have errors." Appellants argue Strasser's "voltage levels of storage cells
[that] may shift over time" do not teach or suggest "that an ECC algorithm
(asserted as corresponding to the claimed code rate) is a function of, or
selected based on, such a shift." App. Br. 10. We agree with the
Examiner's findings that Strasser's "using a robust ECC algorithm ...
allows the life of the solid-state storage media 110 to be extended" and
Strasser's "memory 'may be written approximately 100,000 times without
error per erase cycle' [and that this] 'usage limit may be extended using a
robust ECC algorithm'" represents "the appropriate code rate to use would
change with the age of the drive and the age of the drive increases errors"
and "the code rate to use would depend on the likelihood of errors." Ans. 3,
12 (citing Strasser i-fi-f 107-108).
Appellants contend Strasser teaches extending a usage limit of a
memory using a robust ECC algorithm, but does not teach determining the
likelihood that the data in the memory will have errors. Reply Br. 8. We
highlight Appellants have not persuasively distinguished the code rate of the
codeword encoded by the robust ECC algorithm selected for the older
memory taught in paragraph 108 of Strasser from "the code rate of the
codeword that is capable of being decoded is a function of a likelihood that
data stored in the memory unit will have errors" as recited in claim 9.
Accordingly, we sustain the rejection of claims 9 and 17 under
35 U.S.C. § 103.
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Appeal2014-007605
Application 13/170,802
Section 103 rejection of claims 2--4, 6, 7, 10, 14, 16, and 18-20
Appellants do not present arguments for separate patentability of
claim 18 (App. Br. 10-11) or for claims 2--4, 6, 7, 10, 14, 16, 19, and 20 (Br.
11), which fall with claims 1, 8, 9, 13, and 17.
We sustain the rejection of claims 2--4, 6, 7, 10, 14, 16, and 18-20
under 35 U.S.C. § 103.
DECISION
The Examiner's rejections of claims 1--4, 6-14, and 16-20 are
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv). See
37 C.F.R. § 41.50(f).
AFFIRMED
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