Ex Parte Park et al

Patent Trial and Appeal Board

May 23, 2013

11951525 (P.T.A.B. May. 23, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte HYE-HYANG PARK and BYOUNG-DEOG CHOI
____________

Appeal 2011-005686
Application 11/951,525
Technology Center 2800
____________

Before JOSEPH L. DIXON, ST. JOHN COURTENAY III, and
CARLA M. KRIVAK, Administrative Patent Judges.

COURTENAY, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-005686
Application 11/951,525
2
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from a rejection of claims 1,
2, 4-13, and 15-22. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

INVENTION
The claims are directed to a thin film transistor, a method of
fabricating the thin film transistor, and an organic light emitting diode
display device (OLED display device) including the thin film transistor.
Claim 1, reproduced below, is representative of the claimed subject matter:
1. A thin film transistor comprising:

a substrate;

a semiconductor layer disposed on the substrate;

a gate insulating layer disposed on the semiconductor
layer, and formed entirely of a thermal oxide layer having a
thickness of 50Å - 300Å and patterned such that boundaries of
the thermal oxide layer align with the boundaries of the
semiconductor layer;

a gate electrode disposed directly on the thermal oxide
layer that forms the gate insulating layer, and disposed to
correspond to a predetermined region of the semiconductor
layer;

an interlayer insulating layer disposed on an entire
surface of the substrate; and

source and drain electrodes electrically connected to the
semiconductor layer.

Appeal 2011-005686
Application 11/951,525
3
REFERENCES
The prior art relied upon by the Examiner as evidence in rejecting the
claims on appeal is:
Hirano US 5,771,110 Jun. 23, 1998
Hamada US 6,329,269 B1 Dec. 11, 2001
Horikoshi US 2002/0113264 Al Aug. 22, 2002
Park US 2005/0046342 Al Mar. 03, 2005
Kunii US 2006/0051903 Al Mar. 09, 2006
Lee KR 10-2005-0110345 Nov. 23, 2005
Hong WO 2006/031017 Al Mar. 23, 2006

REJECTIONS
R1. Claims 1, 2, 4, and 16-22 stand rejected under 35 U.S.C § 103(a)
as being unpatentable over the combination of Lee and Horikoshi.
R2. Claims 5-7, 9, 11, 19, and 20 stand rejected under 35 U.S.C
§ 103(a) as being unpatentable over the combination of Lee, Horikoshi, and
Hong.
R3. Claim 8 stands rejected under 35 U.S.C § 103(a) as being
unpatentable over the combination of Lee, Horikoshi, Hong, and Hirano.
R4. Claim 10 stands rejected under 35 U.S.C § 103(a) as being
unpatentable over the combination of Lee, Horikoshi, Hong, and Kunii.
R5. Claims 12, 13, and 15 stand rejected under 35 U.S.C § 103(a) as
being unpatentable over the combination of Park, Lee, and Horikoshi.

ANALYSIS
We disagree with Appellants' contentions regarding the Examiner's
obviousness rejections of the claims. We adopt as our own: (1) the findings
and reasons set forth by the Examiner in the action from which this appeal is
Appeal 2011-005686
Application 11/951,525
4
taken, and (2) the reasons set forth by the Examiner in the Answer in
response to arguments made in Appellants' Appeal Brief. (Ans. 18-25). We
highlight and address specific findings and arguments below.

CLAIMS 1, 16, AND 19
A.
Appellants contend the Examiner is incorrect in finding that Horikoshi
teaches or suggests "a gate insulating layer . . . formed entirely of a thermal
oxide layer having a thickness of 50Å - 300Å" as recited in claim 1 and
commensurate language in claims 16 and 19. (Reply Br. 4). Specifically,
Appellants contend that Horikoshi does not teach the thickness of the gate
insulating layer in the single layer structure. (Id.).
Appellants' contentions are not persuasive. Horikoshi’s paragraph
[0046] teaches "the step of forming the second insulating layer 6b may only
be omitted in the steps described above [for the two layer structure 6a 6b]."
In the step above (¶ [0040]) for the silicon oxide layer 6a, Horikoshi teaches
the silicon oxide layer 6a has a thickness of 40 Å or larger. Horikoshi
teaches that single layer embodiment only omits the step of forming the
second insulating layer 6b and does not teach changing the step of forming
the thermal silicon oxide layer to a thickness of 40 Å or larger. (¶ [0046]).
We agree with the Examiner that Horikoshi's teaching of the silicon oxide
layer with a thickness of 40 Å or larger would have taught or suggested the
claimed 50 to 300 Å range.1

1 As the Court of Appeals for the Federal Circuit held: “[w]here a claimed
range overlaps with a range disclosed in the prior art, there is a presumption
of obviousness.” Ormco Corp. v. Align Technology, Inc., 463 F.3d 1299,
Appeal 2011-005686
Application 11/951,525
5
Appellants' contention that Horikoshi's Figure 4 shows a single gate
oxide layer 6 having the same thickness as the two layers 6a and 6b in
Figure 1 is not persuasive. (Reply Br. 3). Horikoshi's Figures are not to
scale and do not show dimensions. (See Horikoshi, Figures 1 and 4;
¶ [0040]).2 Therefore, Horikoshi's Figures cannot be relied upon to
determine the thickness of layer 6. For these reasons, on this record, we are
not persuaded of Examiner error.
B. Separate arguments for claim 19
Appellants contend that Hamada does not teach or suggest "[a]
forming a thermal oxide layer . . . so as to function as a gate insulating
layer; [b] wherein a complete forming of the polysilicon and the forming of
the thermal oxide layer are carried out simultaneously by annealing the
amorphous silicon layer in an H20 atmosphere." (Reply Br. 6). Appellants'
contention is not persuasive because the Examiner only relies on official
notice using Hamada as evidentiary support to teach or suggest limitation
[b], not [a]. (Ans. 23). Appellants do not rebut the Examiner's proffered
combination of references.
Appellants' contention that the benefits of the thermal silicon oxide
layer 6a (Horikoshi ¶[0075]) do not apply to Horikoshi's single silicon oxide
layer embodiment is not persuasive. (Reply Br. 6-7). The physical and

1311 (Fed. Cir. 2006) (citations omitted). The overlap need not be
substantial to trigger the presumption. In re Geisler, 116 F.3d 1465, 1469
(Fed. Cir.1997).
2 When the reference does not disclose that the drawings are to scale and is
silent as to dimensions, arguments based on measurement of the drawing
features are of little value. See Hockerson-Halberstadt, Inc. v. Avia Group
Int’l., Inc., 222 F.3d 951, 956 (Fed. Cir. 2000).
Appeal 2011-005686
Application 11/951,525
6
electrical benefits of the thermal oxide layer 6a (as taught by Horikoshi's
paragraph [0075]) also apply to Horikoshi's single thermal silicon oxide
layer embodiment because the single silicon oxide layer embodiment
includes the single thermal silicon oxide layer 6a. (Ans. 24). Appellants do
not rebut the Examiner's finding. For these reasons, on this record, we are
not persuaded of Examiner error.

CLAIM 5
Appellants contend that Lee does not teach or suggest the limitation of
"patterning the polysilicon layer and the thermal oxide layer to respectively
form a semiconductor layer and a gate insulating layer" and "forming a gate
electrode directly on the thermal oxide layer," as recited by independent
claim 5. (App. Br. 12; Reply Br. 8). Specifically, Appellants contend that
both Lee's thermal oxide film (225a) and chemical vapor deposition (CVD)
isolation layer (230) correspond to the "gate insulating layer." (Id.).
Appellants' contentions are not persuasive because Appellants attack
the references individually.3 (Id.). The Examiner relies on Lee to teach the
claimed patterning and on Lee's thermal oxide film (225a) to teach or
suggest the claimed "gate insulating layer." (Ans. 9-10). Moreover, the
Examiner relies on the combination of Lee's thermal oxide film (225a) and
Horikoshi's single gate insulating layer 6 (Figure 4). (Id.). Thus, the
Examiner relies on the combination of Lee and Horikoshi to teach or suggest

3 One cannot show nonobviousness by attacking references individually
where the rejections are based on combinations of references. In re Merck
& Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986).

Appeal 2011-005686
Application 11/951,525
7
that the gate electrode is formed directly on the gate insulating layer. (Ans.
10). For these reasons, on this record, we are not persuaded of Examiner
error.

REMAINING CLAIMS
Although Appellants present nominal separate arguments for rejected
claims not addressed above, we affirm the Examiner's rejections of all
rejected claims for the reasons set forth by the Examiner in the Answer and
for the reasons discussed above regarding commensurate limitations and
issues.

DECISION
We affirm the Examiner's rejections R1-R5 of claims 1, 2, 4-13, and
15-22 under § 103.
No time for taking any action connected with this appeal may be
extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

llw