Ex Parte Osakabe et al

Board of Patent Appeals and Interferences

Apr 6, 2010

10942023 (B.P.A.I. Apr. 6, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte TAKESHI OSAKABE, HIROYUKI KAWAGUCHI,
YOSHITAKA UEDA, and SHUJI TAKAHASHI
____________________

Appeal 2009-001747
Application 10/942,0231
Technology Center 2100
____________________

Decided: April 6, 2010
____________________

Before JAY P. LUCAS, CAROLYN D. THOMAS, and JAMES R.
HUGHES, Administrative Patent Judges.

LUCAS, Administrative Patent Judge.

DECISION ON APPEAL

1 Application filed September 16, 2004. Appellants claim the benefit under
35 U.S.C. § 119 of Japan application 2003-327160, filed 9/19/03. The real
party in interest is NEC Electronics Corporation.
Appeal 2009-001747
Application 10/942,023
STATEMENT OF THE CASE
Appellants appeal from a final rejection of claims 1 to 48 under
authority of 35 U.S.C. § 134(a). The Board of Patent Appeals and
Interferences (BPAI) has jurisdiction under 35 U.S.C. § 6(b).
We affirm the rejection.

Appellants’ invention relates to a system and method for efficiently
writing data to blocks of an EEPROM (electronically erasable
programmable read only memory). In the words of Appellants:
[T]he write unit sequentially writes the data to the
block from an area next to an area where data is
stored. When reading data from the block, the
read unit sequentially searches the block from top
or end to find an area where data is written last,
and reads the data stored in the area.
According to a second aspect of the present
invention, there is provided the data read/write
control system of the first aspect, wherein, in
writing data to the block, the write unit further
writes control data including information on
reading of the data before or after the data.
According to a third aspect of the present
invention, there is provided a data read/write
control system including memory, a control data
storage unit, a write unit, and a read unit. The
memory is divided into a plurality of blocks. The
control data storage unit stores control data
including information on reading of data stored in
one block of the plurality of blocks. When writing
data to one block of the plurality of blocks, a write
unit compares a size of the data with a capacity of
a blank area of the block. If the size of the data is
larger, the write unit erases all data stored in the
block, sequentially writes the data to the block
from top or end, and further writes control data of
the written data to the control data storage unit. If,
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Appeal 2009-001747
Application 10/942,023
on the other hand, the size of the data is smaller,
the write unit sequentially writes the data to the
block from an area next to an area where data is
stored and further writes control data of the written
data to the control data storage unit. When reading
data from the block, the read unit sequentially
searches the block for an area where data is written
last based on the control data stored in the control
data storage unit and reads the data stored in the
area.
(Spec. 2, l. 11 to 3, l. 14)

Claim 1 is exemplary, and is reproduced below:
1. A data read/write control system
comprising:

memory divided into a plurality of blocks;

a write unit for, in writing data to one block
of the plurality of blocks, comparing a size of the
data with a capacity of a blank area of the block,
and, if the size of the data is larger, the write unit
erasing all data stored in the block and sequentially
writing the data to the block from top or end;

if the size of the data is smaller, the write
unit sequentially writing the data to the block from
an area next to an area where data is stored; and

a read unit for, in reading data from the
block, sequentially searching the block from top or
end for an area where data is written last and
reading the data stored in the area.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
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Appeal 2009-001747
Application 10/942,023
Hasbun US 5,563,828 Oct. 8, 1996
Fujio US 6,189,081 B1 Feb. 13, 2001
REJECTION
The Examiner rejects the claims as follows:

Claims 1 to 48 stand rejected under 35 U.S.C. § 103(a) for being obvious
over Hasbun in view of Fujio.

Appellants contend that the claimed subject matter is not rendered
obvious by Hasbun in combination with Fujio for failure of the references to
teach claimed limitations. The Examiner contends that each of the claims is
properly rejected.
The rejections will be reviewed in the order argued by Appellants.
Claim 1 is representative. Only those arguments actually made by
Appellants have been considered in this opinion. Arguments that Appellants
could have made but chose not to make in the Briefs have not been
considered and are deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(vii).

ISSUE
The issue is whether Appellants have shown that the Examiner erred
in rejecting the claims under 35 U.S.C. § 103(a). The issue specifically turns
on whether Hasbun and Fujio teach writing user data to blocks of an
EEPROM by comparing the available space in the memory and, if it is not
sufficient to hold the user data, erasing the old data in the block before
writing.

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Appeal 2009-001747
Application 10/942,023
FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
1. Appellants have invented a system and method to use an EEPROM as a
flash memory to hold blocks of data in a computer environment (Spec. 1,
middle). When writing user data to an EEPROM, the invention reads
the memory from one end to find a blank area (Spec. 17, bottom). If the
CPU determines that the size of the new user data is smaller than the
capacity of the blank area, it writes the user data in the blank area next to
a non-blank address (Spec. 18, top). If the user data is bigger than the
blank area in the block, the system erases the block and writes to it (Id.).
2. Hasbun teaches a system which writes data to an EEPROM bank divided
into logical storage blocks 31 (Fig. 3; Col. 6, ll. 30 to 60). Read and
write commands from a logic circuit 22 are executed by a microcontroller
under the control of a command user interface (Col. 5, ll. 63 to 65).
3. Fujio teaches a system and method for writing data to EEPROM flash
memories (Col. 1, l. 40). Blocks of memory 40 are configured so that the
flash memory can be erased in units of blocks, which may be of different
sizes, e.g. 64 KB or 8 KB (Col. 2, ll. 38, 50). The size of the data to be
written is compared to the size of available writable storage in the erase
blocks (Col. 5, ll. 50 to 60).

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Appeal 2009-001747
Application 10/942,023
PRINCIPLES OF LAW
Appellants have the burden on appeal to the Board to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a
rejection [under § 103] by showing insufficient evidence of prima facie
obviousness or by rebutting the prima facie case with evidence of secondary
indicia of nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355
(Fed. Cir. 1998)).

“In reviewing the [E]xaminer’s decision on appeal, the Board must
necessarily weigh all of the evidence and argument.” In re Oetiker, 977
F.2d 1443, 1445 (Fed. Cir. 1992).
“[T]he words of a claim ‘are generally given their ordinary and
customary meaning.’” Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed.
Cir. 2005) (en banc) (internal citations omitted). “[T]he ordinary and
customary meaning of a claim term is the meaning that the term would have
to a person of ordinary skill in the art in question at the time of the invention,
i.e., as of the effective filing date of the patent application.” Id. at 1313.

ANALYSIS
From our review of the administrative record, we find that the
Examiner presents his evidence for a prima facie case on pages 3 to 16 of the
Examiner’s Answer. In opposition, Appellants present a number of
arguments.

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Appeal 2009-001747
Application 10/942,023
Arguments with respect to the rejection
of claims 1 to 48
under 35 U.S.C. § 103

The Examiner has rejected the noted claims for being obvious over
Hasbun in view of Fujio. Appellants first argue “that neither Hasbun nor
Fujio suggests comparing size of data with the size of the blank area within a
block.” (App. Br. 11, middle) (emphasis omitted). In the rejection, the
Examiner relies on Fujio, citing an example in which the system compares
the blocks one after another to find one with sufficient blank area to hold a
36 Kbyte section of data to be written (Col. 9, ll. 44 to 54). Appellants in
turn argue that Fujio is not “data reading to determine blank space size”
(App. Br. 11, middle), but we agree with the Examiner—no such limitation
is in the claims.
The Appellants then argue that there is no indication in either
reference of erasing all data stored in the block if the new data to be written
is too large for the blank space remaining in a block (App. Br. 12, top).
Fujio teaches seeking an empty erase-block to place the data when the data
is too large to fit into available space in another block. (Fujio, col. 9, l. 42).
Hasbun also teaches erasing a block of data when needed to store more
information than the available space can hold (Hasbun, col. 6, ll. 40 to 47).
Both references also teach directly writing the new data if the space is
available (Hasbun, col. 8, l. 55; Fujio, col. 9, ll. 38 to 54). We find these
teachings sufficient to support the Examiner’s rejections.
Finally, the Appellants traverse the combination of Hasbun and Fujio
in this rejection, contending that they are not analogous art. We adopt the
response of the Examiner to this argument and do not find Appellants’
argument convincing (Ans. 16 to 19).
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Appeal 2009-001747
Application 10/942,023

CONCLUSIONS OF LAW
Based on the findings of facts and analysis above, we conclude that
the Examiner did not err in rejecting claims 1 to 48.

DECISION
The Examiner’s rejection of claims 1 to 48 under 35 U.S.C. § 103(a)
is affirmed.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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