Ex Parte Opiniano

Patent Trial and Appeal Board

Mar 27, 2018

14157817 (P.T.A.B. Mar. 27, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/157,817 01/17/2014
75359 7590
ZILKA-KOTAB, PC-NVID
1155 N. 1st St.
Suite 105
SAN JOSE, CA 95112
03/29/2018
FIRST NAMED INVENTOR
Ernesto A. OPINIANO
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
NVIDP966/13-SC-0421-US1 6902
EXAMINER
NGO,NGANV
ART UNIT PAPER NUMBER
2819
NOTIFICATION DATE DELIVERY MODE
03/29/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
zk-uspto@zilkakotab.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ERNESTO A. OPINIANO
Appeal2017-007555
Application 14/157 ,817
Technology Center 2800
Before BRADLEY R. GARRIS, JEFFREY W. ABRAHAM, and
MONTE T. SQUIRE, Administrative Patent Judges.
SQUIRE, Administrative Patent Judge.
DECISION ON APPEAL 1
Appellant2 appeals under 35 U.S.C. § 134(a) from the Examiner's
final rejection of claims 1-3, 5, and 6, which constitute all the claims
pending in this application. We have jurisdiction under 35 U.S.C. § 6(b ).
We REVERSE.
1 In our Decision, we refer to the Specification filed January 17, 2014
("Spec."); Final Office Action dated May 19, 2016 ("Final Act."); Appeal
Brief filed November 14, 2016 ("Appeal Br."); Examiner's Answer dated
February 17, 2017 ("Ans."); and Reply Brief filed April 17, 2017 ("Reply
Br.").
2 Appellant is Applicant NVIDIA Corporation, which, according to the
Appeal Brief, is also identified as the real party in interest. Appeal Br. 3.
Appeal2017-007555
Application 14/157,817
The Claimed Invention
Appellant's disclosure relates to a method of forming a package on
package, semiconductor package arrangement. Spec. i-f 4, Abstract. Claim 1
is illustrative of the claimed subject matter on appeal and is reproduced
below from the Claims Appendix to the Appeal Brief (Appeal Br. 13)
(indentation added) (key disputed claim language italicized and bolded):
1. A method of packaging integrated circuits
compnsmg:
providing a first grid array package having a first
substrate, a first die mounted on the first substrate and a
multiplicity of first solder bumps on a lower surface of
the first substrate, the multiplicity of first solder bumps
being exposed at the lower surface of the first grid array
package;
providing a second grid array package having a
second substrate, a second die flip chip mounted on a top
surface of the second substrate, and a multiplicity of third
solder bumps on the top surface of the second substrate,
wherein the multiplicity of second solder bumps are
exposed at a lower surface of the second grid array
package, wherein the multiplicity of third solder bumps
have a spacing that matches a spacing of the first solder
bumps, and wherein no molding material is provided on
the top surface of the second substrate;
fusing the first solder bumps to corresponding ones
of the third solder bumps to thereby form solder joints
that electrically couple the first grid array package to the
second grid array package and to thereby form a stacked
package on package, wherein the respective sizes of the
first and third solder balls are arranged such that a height
of the resulting solder joints is greater than the height of
the second die such that the first substrate does not
contact any portion of the second package and an air gap
is formed that separates the second die from the first
package.
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Appeal2017-007555
Application 14/157,817
The References
The Examiner relies on the following prior art references as evidence
in rejecting the claims on appeal:
Corisis et al., US 6,072,233 June 6, 2000
(hereinafter "Corisis")
Lee et al., US 2006/0110849 Al May 25, 2006
(hereinafter "Lee")
Roberts et al., US 7,868,440 B2 Jan. 11, 2011
(hereinafter "Roberts")
The Rejections
On appeal, the Examiner maintains (Ans. 2) the following rejections:
1. Claims 1, 3, and 5 are rejected under 35 U.S.C. § 103 as being
unpatentable over Lee in view of Corisis ("Rejection 1 "). Final Act. 2-3.
2. Claims 2 and 6 are rejected under 35 U.S.C. § 103 as being
unpatentable over Lee in view of Corisis and further in view of Roberts
("Rejection 2"). Final Act. 3
OPINION
Rejection 1
The Examiner determines that the combination of Lee and Corisis
suggests a method of packaging integrated circuits, satisfying all of the steps
of claim 1, and thus, concludes that the combination would have rendered
the claim obvious. Final Act. 2-3 (citing Lee, Figs. 2A-2D (elements 211,
212, 213, 219, 221, 222, 223), i-f 20; Corisis, Fig. 1 ).
Appellant argues that the Examiner's rejection of claim 1 should be
reversed because neither Lee nor Corisis, taken alone or in combination,
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Application 14/157,817
discloses or suggests "no molding material being provided on the top surface
of the second substrate," as required by the claim. Appeal Br. 8; see also
Reply Br. 3.
Appellant further argues that the Lee and Corisis references teach
away from a packaging structure having the claimed configuration (Appeal
Br. 8) and there would have been "no motivation to combine the prior art
teachings" in the manner claimed (id. at 7). In particular, Appellant
contends that because both Lee and Corisis disclose that when a top surface
of a substrate has both the die and solder bumps, an encapsulating material
on the top surface is required, "there would be no motivation to modify
Lee's top surface having both the die and solder bumps in accordance with
Figure 1 ofCorisis." Id. at 10.
We find Appellant's arguments persuasive of reversible error in the
Examiner's rejection because the Examiner has not established by a
preponderance of the evidence that the combination of Lee and Corisis
discloses or suggests "no molding material being provided on the top surface
of the second substrate," as required by claim 1. In re Oetiker, 977 F.2d
1443, 1445 (Fed. Cir. 1992) (holding that the examiner bears the initial
burden of establishing a prima facie case of obviousness).
None of the portions of Lee that the Examiner relies upon in the
rejection disclose or suggest this limitation. See Lee, Figs. 2A-2D, i-f 20.
Rather, as Appellant correctly points out (Appeal Br. 8), and in contrast to
the claimed invention, Lee actually discloses packaging structures having
molding material, i.e., encapsulation, on the top surface of the second
substrate. Id. at i-fi-117, 20, Figs. 2A, 2C, 2D. For example, Figure 2A of Lee
shows a BGA package 210 having solder bumps 213 on both the top and
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Application 14/157,817
bottom surfaces and requiring molding/encapsulation 218 on the top surface
214 of the substrate 211. Lee discloses that "a plurality of first connecting
wires 217 are used for connecting the first chip 212 and the first substrate
211, and encapsulated with the first chip 212 by the first encapsulation 218."
Id. at i-f 17.
Figure 2C of Lee similarly shows a BGA package 220 requiring the
first encapsulation 218 on the top surface of the second substrate 211. Lee i1
20, Fig. 2C. Lee's teaching in this regard is also consistent with Appellant's
disclosure in the Specification regarding prior art BGA packages requiring a
molding/encapsulating material on the top surface of the substrate to protect
the semiconductor die, stiffen the package and reduce warping, and the
drawbacks of such a structure. See Spec. i1 3. There is no teaching or
suggestion by Lee of a package structure with "no molding material being
provided on the top surface of the second substrate," as required by claim 1.
The Corisis reference also teaches BGA package structures having
molding/encapsulating material on the top surface of the substrate. Corisis,
col. 5, 11. 44--46, Fig. 6. For example, Figure 6 of Corisis shows a structure
having molding/encapsulating material 26 on the top surfaces of both a first
and second substrate. Corisis discloses that:
Encapsulating material 26 is then provided to cover the
semiconductor die 14, wire bonds 22, bond pads 18 and
terminal pads 20.
Id. at col. 5, 11. 44--46.
As Appellant correctly points out (Appeal Br. 10-11), Figure 1 of
Corisis also shows a structure with molding/encapsulating material 26 albeit
located in the spacing between the bottom surface of the first substrate 12
and the top surface of the second substrate. Although Figure 1 of Corisis
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Application 14/157,817
does not depict the molding/encapsulating material 26 in that embodiment as
being located strictly on the top surface of the second substrate and
completely covering the semiconductor die 14, the reference does teach that
at least a "portion of semiconductor die 14 ... is covered by an
encapsulating material 26" (Corisis, col. 4, 11. 18-21 ).
The Corisis reference also teaches that
Encapsulating material protects both the IC device and the wire
interconnect as the conductive elements make contact with the
FBGA position below or above to form a stack ... and an
encapsulant is used to contain the IC device and wires within
and below the matrix and profile of the conductive elements.
Corisis, col. 2, 11. 46-55.
Moreover, on the record before us, we are not persuaded that the
Examiner identifies evidence or provides reasoning sufficient to support a
finding that one of ordinary skill would have had reason to modify Lee's
BGA package structure to remove the molding/encapsulation material on the
top surface of the second substrate, as would be required to arrive at the
claimed invention. See KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398, 418
(2007) (requiring "reasoning with some rational underpinning to support the
legal conclusion of obviousness") (quoting In re Kahn, 441 F.3d 977, 988
(Fed. Cir. 2006)).
In particular, the Examiner does not persuasively respond to
Appellant's argument regarding the cited references both disclosing
structures requiring the use of molding/encapsulating material or direct us to
any teaching or suggestion in the prior art regarding the technical feasibility
of removing the molding/encapsulation material from the top surface of the
second substrate; the impact that would have on the operation of the Lee's
package; or why one of ordinary skill in the art would have had a reasonable
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Application 14/157,817
expectation of success in modifying Lee's package in such a manner. For
example, the Examiner provides no discussion regarding what impact such a
modification would have on protecting the semiconductor components,
stiffening the package, and/or reducing warping.
The Examiner's statement that "less molding material is needed to
cover the connecting wires than the semiconductor die, thus saving time and
money during manufacture of the stacked devices" (Ans. 3), without more,
is insufficient to sustain the Examiner's rejection. Kahn, 441 F.3d at 988
(holding "rejections on obviousness grounds cannot be sustained by mere
conclusory statements").
We, therefore, cannot sustain the Examiner's rejection of claim 1 and
determination that it would have been obvious to combine the teachings of
Lee and Corisis to arrive at the claimed subject matter with a reasonable
likelihood of success.
Because claim 3 depends from claim 1 and claim 5 recites the same
"wherein no molding material is provided on the top surface of the second
substrate" limitation as claim 1, we also cannot sustain the Examiner's
rejection of these claims.
Accordingly, we reverse the Examiner's rejection of claims 1, 3, and 5
under 35 U.S.C. § 103 as obvious over the combination of Lee and Corisis.
Rejection 2
The foregoing deficiencies in the Examiner's analysis and conclusion
regarding the combination of Lee and Corisis are not remedied by the
Examiner's findings regarding the additional reference or combination of
references cited in support of the second ground of rejection.
Accordingly, we also reverse the Examiner's Rejection 2.
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Application 14/157,817
DECISION/ORDER
The Examiner's rejections of claims 1-3, 5, and 6 are reversed.
It is ordered that the Examiner's decision is reversed.
AFFIRMED
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