Ex Parte Olukotun

Board of Patent Appeals and Interferences

Jun 13, 2012

10855694 (B.P.A.I. Jun. 13, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/855,694 05/26/2004 Kunle A. Olukotun SUNMP362 8901
32291 7590 06/14/2012
MARTINE PENILLA GROUP, LLP
710 LAKEWAY DRIVE
SUITE 200
SUNNYVALE, CA 94085
EXAMINER
THAI, TUAN V
ART UNIT PAPER NUMBER
2185
MAIL DATE DELIVERY MODE
06/14/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte KUNLE A. OLUKOTUN
____________________

Appeal 2010-002135
Application 10/855,694
Technology Center 2100
____________________

Before ERIC S. FRAHM, DAVID M. KOHUT, and JOHNNY A. KUMAR,
Administrative Patent Judges.

FRAHM, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF CASE
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 1-12, 14-17, and 19-21. Claims 13 and 18 have been canceled. We
have jurisdiction under 35 U.S.C. § 6(b). We affirm.
Exemplary Claim
Appellant’s invention relates to processor architecture, and to a
processor chip to efficiently process server applications (Spec. ¶ [0007]).
Appellant discloses and claims a server having an application processor chip
which includes a plurality of multi-threaded processing cores, plural cache
bank memories, and a crossbar having an arbiter to sort requests from
different ones of the processing cores to enable communication between
different ones of the processing cores and the cache bank memories (Spec.
¶¶ [0008]-[0010]; Abs.; claims 1, 10, and 15).
Exemplary independent claim 1 under appeal, with emphasis added,
reads as follows:

1. A processor chip, comprising:

a plurality of processing cores, each of the processing cores being
multi-threaded, the plurality of processing cores being located in a center
region of the processor chip;

a plurality of cache bank memories;

a first crossbar enabling communication between a first portion of the
plurality of processing cores and the plurality of cache bank memories, the
first crossbar including an arbiter configured to sort multiple requests
received from the first portion of the plurality of processing cores, and

a second crossbar enabling communication between a second portion
of the plurality of processing cores and the plurality of cache bank
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memories, the second crossbar including an arbiter configured to sort
multiple requests received from the second portion of the plurality of
processing cores.
The Examiner’s Rejections
(1) The Examiner rejected claims 1-12, 14-17, and 19-21 under 35
U.S.C. § 112, first paragraph, as failing to provide adequate written
description of the claimed invention, i.e., failing to describe more than one
crossbar in such a way as to reasonably convey to one skilled in the art that
the inventor had possession of the currently claimed invention at the time the
application was filed. Ans. 3-4. The Examiner determines that the
originally filed Specification and Drawings fail to show, describe, and/or
provide written description support for more than one crossbar (Ans. 3-4 and
12). The Examiner finds (Ans. 3-4) that Appellant’s Specification (Spec. ¶
[0028]) only describes a single crossbar (see Figs. 4A-4C, crossbar 182), and
that Figure 5B is described as only having a single crossbar (Spec. ¶ [0031]).
The Examiner also determines (Ans. 4 and 12) that the Specification
describes a distributed design with a single crossbar (Spec. ¶ [0034]; Fig.
5B, crossbar 194), the crossbar having multiple arbiters (Ans. 12 citing col.
2 of Table 1 at Spec. 14-15).
(2) The Examiner rejected claims 2, 8, 9, 11, 12, 16, and 17 under 35
U.S.C. § 112, second paragraph, as being indefinite for failing to particularly
point out and distinctly claim what Appellant considers to be the invention.
Ans. 4-5. The Examiner determines (Ans. 4-5) that the term “the crossbar”
in claims 2, 8, 9, 11, 12, 16, and 17 lacks antecedent basis because it is
unclear if this term is referring back to the first crossbar or the second
crossbar recited in the respective independent claims.
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(3) The Examiner rejected claims 1, 3-12, 15-17, 20, and 21 as being
unpatentable under 35 U.S.C. § 103(a) over Kohn (WO 03/036482 A2),
Johnson (US 4,627,050), and Tanaka (US 6,789,173 B1). Ans. 5-9. For
purposes of applying the references to the claims, the Examiner interprets
claims 1-12, 14-17, and 19-21 as reciting first and second crossbars, and
relies upon Tanaka as teaching a first crossbar (element 1-0 in Fig. 1) and a
second crossbar (element 1-1 in Fig. 1), as set forth in claims 1, 10, and 15
(see, e.g., Ans. 7-8) .
(4) The Examiner rejected claims 14 and 19 as being unpatentable
under 35 U.S.C. § 103(a) over Kohn, Johnson, Tanaka, and Chaudhry (US
2002/0188807 A1). Ans. 9.
(5) The Examiner rejected claim 2 as being unpatentable under
35 U.S.C. § 103(a) over Kohn, Johnson, Tanaka, and Kapur (US
2003/0163649 A1). Ans. 10-11.
Appellant’s Contentions1
(1) Appellant contends (Br. 5-6) that the Examiner erred in rejecting
claims 1-12, 14-17, and 19-21 under 35 U.S.C. § 112, first paragraph,
because first and second crossbars are adequately supported by Figures 4B,
5B, and paragraph [0034] (making reference to “crossbars”). Appellant
further argues (Br. 6) that plural crossbars 194 are shown in Figure 5B.

1 Appellant does not provide separate patentability arguments for claims 14
and 19 rejected under 35 U.S.C. § 103(a) over Kohn, Johnson, Tanaka, and
Chaudhry, and instead argues these claims with claims 1, 3-12, 15-17, 20,
and 21 rejected under 35 U.S.C. § 103(a) over Kohn, Johnson, and Tanaka
(see Br. 6).
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(2) With regard to the rejection of claims 2, 8, 9, 11, 12, 16, and 17
under 35 U.S.C. § 112, second paragraph, as being indefinite, “Appellant
asserts that the use of the term ‘the crossbar’ is due to clerical error” (Br. 6),
but does not allege any error in the Examiner’s rejection.
(3) Appellant contends (Br. 6-10) that the Examiner erred in rejecting
claims 1, 3-12, 15-17, 20, and 21 under 35 U.S.C. § 103(a) over Kohn,
Johnson, and Tanaka for numerous reasons, including:
(a) with regard to claims 1, 10, and 15, Tanaka fails to teach first and
second crossbars, and Kohn is not configured to sort multiple requests (Br.
6-8);
(b) with regard to claim 3, Kohn’s Figure 8 stage is part of a sequence,
and not a register file, therefore Kohn’s pipeline stage is not equivalent to
the claimed register file (Br. 9-10); and
(c) with regard to claims 1, 4-9, 14, and 21, the prior art fails to
disclose processing cores located in a center region of a processor chip (Br.
8-9).
(4) Appellant contends (Br. 10) that the Examiner erred in rejecting
claim 2 under 35 U.S.C. § 103(a) over Kohn, Johnson, Tanaka, and Kapur
because Kapur fails to teach input/output (I/O) modules in communication
with a main memory interface to provide a link to the plural processing cores
and bypass the crossbar.
Issues on Appeal
Based on Appellant’s arguments, the following issues are presented
on appeal:
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(1) Did the Examiner err in determining that the originally filed
Specification fails to reasonably convey to one of ordinary skill in the art
that Appellant had possession of the claim limitations “first crossbar” and
“second crossbar,” as set forth in claims 1, 10, and 15?
(2) Has Appellant shown that the Examiner erred in rejecting claims
2, 8, 9, 11, 12, 16, and 17 as being indefinite for lack of proper antecedent
bases under § 112, second paragraph?
(3) Did the Examiner err in rejecting claims 1, 3-12, 15-17, 20, and 21
as being obvious because the combination of Kohn, Johnson, and Tanaka
fails to teach or suggest (i) sorting multiple requests and first and second
crossbars as recited in claims 1, 10, and 15; (ii) processing cores located in a
center region of a processor chip as recited in claims 1, 4-9, 14, and 21;
and/or (iii) a register file as recited in claim 3?
(4) Has Appellant shown that the Examiner erred in rejecting claims
14 and 19 as being obvious over the combination of Kohn, Johnson, Tanaka
and Chaudhry?
(5) Did the Examiner err in rejecting claim 2 as being obvious because
the combination of Kohn, Johnson, Tanaka, and Kapur fails to teach or
suggest the I/O modules as set forth in that claim?

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
arguments in the Appeal Brief (App. Br. 5-11) that the Examiner has erred.
We do not agree with Appellant’s conclusions.
We adopt as our own (1) the findings and reasons set forth by the
Examiner in the action from which this appeal is taken, and (2) the reasons
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set forth by the Examiner in the Examiner’s Answer in response to
Appellant’s Appeal Brief (see Ans. 3-14), with the exception that we
disagree with the Examiner’s statement (Ans. 4) that the Specification fails
to once use the term “crossbars” in the plural form. We concur with the
conclusions reached by the Examiner, and highlight and address specific
findings and arguments for emphasis as follows.
Issue (1): § 112, First Paragraph, Rejection
We disagree with Appellant that the originally filed Specification
reasonably conveys to one of ordinary skill in the art that Appellant had
possession of the claim limitations “first crossbar” and “second crossbar,” as
recited in claims 1, 10, and 15 on appeal. We also disagree with the
Examiner’s statement that a “text search for ‘crossbar’ in the specification
has failed to yield even one instance of crossbar in plural or even a mention
of having more than one” (Ans. 4), because paragraph [0034] describes that
“[f]or the distributed cases, the crossbars have been designed to handle a
selection of 16 references per cycle, evenly distributed among the processors
and cache banks” (Spec. ¶ [0034] (emphasis added)).
However, we agree with the Examiner (Ans. 4 and 12) that paragraph
[0034] describes a crossbar in multiple embodiments, paragraph [0037]
describes several crossbar stages, and column 2 of TABLE 1 (Spec. 14-15)
provides listings of different distributed crossbar designs. Thus, Appellant’s
originally filed Specification only provides a written description supporting
a distributed crossbar design including only a single crossbar (even if the
crossbar has different segments/stages).
Furthermore, we find that the Specification as originally filed
discloses a single crossbar 182 in Figures 4A and 4B (Spec. ¶¶ [0028] and
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[0029]); and only a single crossbar 194 having an H shaped layout in Figure
5B (Spec. ¶ [0033]). The originally filed Abstract (Spec. 24) aligns with
only one crossbar being present (see Abs. l. 4), as do the originally filed
claims (claims 1, 10, and 15 each recite “a crossbar”) and Summary of the
Invention (Spec. ¶¶ [0008]-[0010]). This is also in alignment with what is
shown in Figure 5B, one H shaped crossbar 194. The H shaped crossbar 194
has different stages/segments, but is a single unit. Finally, we note that
Appellant has not defined any element in Figure 4B by reference number as
being the first and/or second crossbars (Br. 2, Summary of Claimed Subject
Matter).
In summary, a review of the entire Specification and Drawings as
originally filed, as a whole, fails to reasonably convey to one of ordinary
skill in the art that Appellant had possession of the claim limitations “first
crossbar” and “second crossbar,” as set forth in independent claims 1, 10,
and 15. Accordingly, we will sustain the Examiner’s rejection of claims 1-
12, 14-17, and 19-21 under 35 U.S.C. § 112, first paragraph.
Issue (2): § 112, Second Paragraph, Rejection
Appellant has not established that the Examiner erred in rejecting
claims 2, 8, 9, 11, 12, 16, and 17 under § 112, second paragraph, as being
indefinite (see Br. 6). Accordingly, we will sustain the § 112, second
paragraph, rejection of claims 2, 8, 9, 11, 12, 16, and 17.
Issue (3): § 103(a) Rejection over Kohn, Johnson, and Tanaka
With regard to claims 1, 10, and 15, the Examiner determines (Ans. 6
and 13) that Kohn’s page 5, line 14 to page 6, line 8 discloses or suggests an
arbiter configured to sort multiple requests, because the crossbar 120
optimizes processor traffic to the memories in Figure 4, and regulates access
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to allow concurrent access to the memories. Appellant’s contention (Br. 7)
that Kohn is silent as to the arbiter being configured to sort multiple requests
is unpersuasive because Kohn’s crossbar 120 optimizes traffic (i.e.,
requests), and suggests sorting the requests by providing concurrent access
and low latency (Kohn at p. 5, ll. 22-31). We agree with the Examiner that
Kohn’s disclosure of keeping the cores busy most of the time, optimizing
traffic, and preventing collisions or excessive delay in the traffic implies or
suggests that the requests are sorted by the crossbar 120, having the same
function as the recited arbiter (Ans. 13 citing Kohn at p. 5, l. 14 – p. 6, l. 8).
Thus, Appellant’s contention (Br. 6-8) that Kohn fails to disclose or suggest
sorting requests at the crossbar is unpersuasive.
Appellant’s contention (Br. 8) that Tanaka fails to teach first and
second crossbars is unpersuasive in light of Tanaka’s Figure 1 which shows
crossbars 1-0 and 1-1.
With regard to claim 3, we agree with the Examiner (Ans. 8 and 14)
that (i) Kohn’s pipeline stages 1-6 shown in Figure 8 and described at page
8, line 22 – page 9, line 4 are equivalent to the recited register files, and (ii)
results from stage 6 “are written to a register file” (Spec. p. 9, ll. 3-4).
With regard to claims 1, 4-9, and 21, we agree with the Examiner
(Ans. 5-6 and 13-14) that (i) Kohn’s Figure 4 shows plural multi-threaded
processing cores 118-1 through 118-8 located outside a center region of the
chip (Fig. 4 as described at p. 5, l. 14 – p. 6, l. 8), and (ii) Kohn’s Figure 6
shows cache memories 122 and 146a-d that surround processors 144a-d on
two sides, and that such an arrangement is equivalent to having processing
cores located in a center region of a processor chip as recited in claims 1, 4-
9, 14, and 21. Kohn shows and describes providing cache memories 122 for
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each of the multi-threaded processor cores located in a center region of the
chip (Fig. 6 as described at p. 8, ll. 1-9; Fig. 4 as described at p. 5, l. 14 – p.
6, l. 8).
In view of the foregoing, the combination of Kohn, Johnson, and
Tanaka teach or suggest (i) sorting multiple requests and first and second
crossbars as recited in claims 1, 10, and 15; (ii) processing cores located in a
center region of a processor chip as recited in claims 1, 4-9, and 21; and/or
(iii) a register file as recited in claim 3. Appellant’s arguments (Br. 6-10) to
the contrary are unpersuasive in view of the Examiner’s findings and
determinations with regard to Kohn, Johnson, and Tanaka (Ans. 5-9 and 13).
Accordingly, we will sustain the Examiner’s rejection of claims 1, 3-12, 15-
17, 20, and 21 under 35 U.S.C. § 103(a) over Kohn, Johnson, and Tanaka.
Issue (4): § 103(a) Rejection over Kohn, Johnson, Tanaka, and Chaudhry
Appellant has not shown that the Examiner erred in rejecting claims
14 and 19 as being obvious under 35 U.S.C. § 103(a) over the combination
of Kohn, Johnson, Tanaka and Chaudhry, or otherwise provided separate
patentability arguments for these claims. Accordingly, we will sustain the
Examiner’s obviousness rejection of claims 14 and 19 for the same reasons
as for claims 10 and 15 from which these claims ultimately and respectively
depend.
Issue (5): § 103(a) Rejection over Kohn, Johnson, Tanaka, and Kapur
We agree with the Examiner (Ans. 10-11 and 14) that Kohn, and not
Kapur (relied upon for teaching bypassing a crossbar), was relied upon in the
rejection under 35 U.S.C. § 103(a) as teaching I/O modules as set forth in
claim 2. Accordingly, Appellant’s contention (Br. 10) that Kapur fails to
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teach I/O modules are unpersuasive since the combination of references,
including Kohn, was applied as teaching or suggesting the subject matter of
claim 2. Accordingly, we will sustain the Examiner’s rejection of claim 2
under 35 U.S.C. § 103(a) over Kohn, Johnson, Tanaka, and Kapur.
CONCLUSIONS
(1) The Examiner did not err in determining that the originally filed
Specification fails to reasonably convey to one of ordinary skill in the art
that Appellant had possession of the claim limitations “first crossbar” and
“second crossbar,” and in rejecting claims 1-12, 14-17, and 19-21 under 35
U.S.C. § 112, first paragraph, as failing to comply with the written
description requirement.
(2) Appellant has not shown that the Examiner erred in rejecting
claims 2, 8, 9, 11, 12, 16, and 17 as being indefinite for lack of proper
antecedent bases under § 112, second paragraph.
(3) The Examiner did not err in rejecting claims 1, 3-12, 15-17, 20,
and 21 as being obvious under 35 U.S.C. § 103(a), because the combination
of Kohn, Johnson, and Tanaka teaches or suggests (i) sorting multiple
requests and first and second crossbars as recited in claims 1, 10, and 15; (ii)
processing cores located in a center region of a processor chip as recited in
claims 1, 4-9, and 21; and/or (iii) a register file as recited in claim 3.
(4) Appellant has not shown that the Examiner erred in rejecting
claims 14 and 19 as being obvious under 35 U.S.C. § 103(a) over the
combination of Kohn, Johnson, Tanaka and Chaudhry, or otherwise
provided separate patentability arguments for these claims.
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(5) The Examiner did not err in rejecting claim 2 as being obvious
under 35 U.S.C. § 103(a) because the combination of Kohn, Johnson,
Tanaka, and Kapur teaches or suggests the I/O modules, as set forth in claim
2.

DECISION
The Examiner's § 112, first paragraph, § 112, second paragraph, and §
103(a) rejections are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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