Ex Parte Olds et al

Board of Patent Appeals and Interferences

Aug 28, 2012

10970424 (B.P.A.I. Aug. 28, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte EDWIN SCOTT OLDS, STEPHEN R. CORNABY,
MARK DAVID HERTZ, and KENNY TROY COKER
____________

Appeal 2010-000491
Application 10/970,424
Technology Center 2100
____________

Before JOSEPH F. RUGGIERO, BRUCE R. WINSOR,
and JENNIFER S. BISK, Administrative Patent Judges.

WINSOR, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-000491
Application 10/970,424

2
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-17, 19-21, and 23-25, which constitute all the claims pending in
this application. Claims 18 and 22 are cancelled. We have jurisdiction
under 35 U.S.C. § 6(b).
We reverse.

STATEMENT OF THE CASE
Appellants’ disclosure “relates generally to command optimization in
a data storage device and more particularly to effectively prioritizing read
and/or write commands in a disc drive.” (Spec. 1:10-11). Claim 1, which is
illustrative of the invention, reads as follows (with the disputed limitation
emphasized):
1. An apparatus for prioritizing the execution of data
transfers into or out of a cache memory, the apparatus
comprising:
a cache memory that receives blocks of data for
temporary storage, wherein each received data block is
associated with a data transfer command sent by a command
device; and
a scheduler that schedules transfers of blocks of data
between the cache memory and a data storage device (DSD),
and schedules transfers of blocks of data between the cache
memory and the command device, wherein the scheduler
assigns a higher level priority to transferring a first data block
associated with a first data transfer command, for which the
apparatus does not need to return a status indicating that the
first data block has been stored in the cache memory, than it
assigns to transferring a second data block associated with a
second data transfer command, for which the apparatus needs
to return a status indicating that the second data block has been
stored in the cache memory.
Appeal 2010-000491
Application 10/970,424

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Claims 1-17, 19-21, and 23-25 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over Stenfort (US 6,591,350 B1; July 8, 2003; filed
Dec. 2, 1999) and Nishtala (US 5,634,068; May 27, 1997).1
Rather than repeat the arguments here, we refer to the Briefs (“App.
Br.;” “Reply Br.”) and the Answer (“Ans.”) for the respective positions of
Appellants and the Examiner.

ISSUE
Appellants’ arguments relate to the patentability of claim 1.
Appellants argue the patentability of claims 17 and 21 based on their
similarity to claim 1 (App. Br. 9-10) and the patentability of claims 2-16, 19,
20, and 23-25 based on their dependence from claim 1, 17, or 21.
Accordingly, we will decide the appeal by referring to claim 1.
The issue raised by Appellants’ contentions is as follows:
Does Nishtala, when combined with Stenfort, teach or suggest
[a] scheduler [that] assigns a higher level priority to transferring
a first data block associated with a first data transfer command,
for which the apparatus does not need to return a status
indicating that the first data block has been stored in the cache
memory, than it assigns to transferring a second data block
associated with a second data transfer command, for which the
apparatus needs to return a status indicating that the second data
block has been stored in the cache memory
(hereinafter the “disputed limitation”), as recited in claim 1?

1 A rejection of claims 21 and 23-25 under 35 U.S.C. § 101 as being directed
to non-statutory subject matter has been withdrawn by the Examiner (Ans.
12).
Appeal 2010-000491
Application 10/970,424

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ANALYSIS
The Examiner finds that Stenfort discloses all the elements of claim 1
except the disputed limitation. (Ans. 4). The Examiner finds that Nishtala
teaches the disputed limitation (Ans. 4-5; see Nishtala col. 61, l. 16–col. 62,
l. 4), and that one of ordinary skill in the art would have found it obvious to
combine Nishtala with Stenfort (Ans. 5). The Examiner explains (Ans. 9)
that Nishtala teaches “master classes” in which class 0 commands are
prioritized over class 1. Nishtala states:
The arbiter circuit 301 selects one inactive transaction request,
giving highest priority to I/O requests (i.e., from an I/O
[Universal Port Architecture (UPA)] port), next highest priority
to master class 0 requests (i.e., read and block load requests),
and lowest priority to master class 1 requests (i.e., writeback
requests, WriteInvalidate requests, block stores, interrupt
requests, and non-cached read/write requests).
(Nishtala col. 61, ll. 21-28).
Each UPA module is required to put in a single master
request class all transaction requests for which ordering is
important. The preferred class assignment for all processor
UPA modules is as follows:
Class 0 is used for read transactions due to cache misses,
and block loads.
Class 1 is used for writeback requests, WriteInvalidate
requests, block stores, interrupt requests, and
noncached read/write requests.
This assignment of memory transactions to classes
enables the memory transactions caused by cache misses to not
be blocked by other transactions and is especially significant
when the data processor supports multiple outstanding loads
and/or prefetching. This gives the lowest possible latency for
cache fills, in conjunction with other optimizations.
(Nishtala col. 15, ll. 45-60).
Appeal 2010-000491
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The Examiner further explains (Ans. 10) that one of ordinary skill in
the art would have understood that a read transaction or a block load
transaction, which are assigned by Nishtala to higher priority master class 0,
would not require an acknowledgement that a block has been written to the
cache memory. The Examiner explains as follows:
Nishtala teaches the writeback requests, and write-invalidate
request transactions[, which are assigned by Nishtala to lower
priority master class 2,] are both required acknowledged to the
system controller and/or the requesting data process to indicate
whether the writeback or write-invalidate requested is
completed or canceled, i.e., status indicated that the transaction
is completed (col. 22 lines 12-40, col. 29 line 51 through col. 30
line 4, and col. 39 lines 33-62), such that the arbiter circuit
functioning as a scheduler to assign a higher level priority to
I/O request for transferring a first data block associated with a
first data transfer command, which the apparatus does not need
to return a status indicating that the first data block has been
stored in the cache memory, than it assigns to transfer a second
block associated with a second data transfer command, such as
write back request, for which the apparatus needs to return a
status indicating that the second data block has been stored in
the cache memory.
(Ans. 9-10).
Appellants contend2 inter alia that:
(1) the passages cited by the Examiner fail to demonstrate that
Nishtala teaches or suggests that a WriteInvalidate command is
a “data transfer command, for which the apparatus needs to
return a status indicating that . . . [a] data block has been stored
in the cache memory,” as recited in claim 1 (Reply Br. 9); and

2 Appellants present additional contentions. As the contentions discussed
herein persuade us of Examiner error and are dispositive of the Appeal, we
do not reach Appellants’ additional contentions.
Appeal 2010-000491
Application 10/970,424

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(2) the Examiner has improperly imported limitations from the
Specification into the claim in determining that Nishtala teaches
or suggests that a writeback request is a “data transfer
command, for which the apparatus needs to return a status
indicating that . . . [a] data block has been stored in the cache
memory,” as recited in claim 1 (Reply Br. 10-11).
We agree with the Examiner (see Ans. 10) that one of ordinary skill in
the art would have understood that at least the read transaction taught by
Nishtala, is a “data transfer command, for which the apparatus does not need
to return a status indicating that the first data block has been stored in the
cache memory,” as recited in claim 1. We agree with Appellants (Reply Br.
9-11), however, that the Examiner has not persuasively demonstrated that
Nishtala teaches or suggests that either the WriteInvalidate command or
writeback command is a “data transfer command, for which the apparatus
needs to return a status indicating that . . . [a] data block has been stored in
the cache memory.”
The Examiner is correct that Nishtala discloses that a reply P_REPLY
is associated with a WriteInvalidate command S_REQ (Nishtala col. 39, ll.
41-46). However, as pointed out by Appellants (App. Br. 9), the passages of
Nishtala cited by the Examiner (Nishtala Fig. 1; col. 4, ll. 27-65; col. 15, ll.
45-60; col. 22, ll. 12-40; col. 29, l. 51–col. 30, l. 4; col. 32, ll. 5-36; col. 39,
ll. 33-62; col. 61, l. 16–col. 62, l. 4) do not persuasively establish that the
reply S_Reply indicates successful completion of a transaction as opposed to
merely acknowledging receipt of the WriteInvalidate command S_REQ.
For emphasis, we note that the passages cited by the Examiner (see
Ans. 4-5, 8-10) additionally do not persuasively establish that a
Appeal 2010-000491
Application 10/970,424

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WriteInvalidate command is intended to cause the transfer of data, i.e., is a
“data transfer command,” or that the reply S_Reply “indicat[es] that . . . [a]
data block has been stored in the cache memory.”
We agree with Appellants that the Examiner has erred by improperly
utilizing Appellants’ Specification in rejecting the claims (App. Br. 9-10;
Reply Br. 10-11). Although we characterize the error differently than do
Appellants, we base our finding of error on the analysis articulated by the
Examiner (Ans. 10-11) that Appellants contend was erroneous.
In finding that Nishtala’s writeback request is a request “for which the
apparatus needs to return a status indicating that . . . [a] data block has been
stored in the cache memory,” the Examiner looks to Appellants’
Specification (Spec. 7-9) to determine that a writeback command is a
command that is considered a non-pending command and that non-pending
commands require the return of a status indicating that a data block has been
stored in the cache memory.3 The Examiner then infers that Nishtala’s
writeback request similarly requires the return of a status indicating that a
data block has been stored in the cache memory. (See generally Ans. 10-
11). The Examiner has not found that the cited passages of the Specification
are admitted prior art, nor has the Examiner articulated any rationale for
combining the cited passages of the Specification with Stenfort and Nishtala.
See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). Such reading
of features from Appellants’ Specification into the prior art is an exercise of
impermissible hindsight and is error.

3 We do not consider whether the Examiner has correctly characterized the
Specification, as that issue is not before us.
Appeal 2010-000491
Application 10/970,424

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For emphasis we note that Nishtala defines a “writeback” as “copying
modified data from a cache memory into main memory.” (Nishtala col. 4, ll.
6-7 (emphasis added)). Thus, Nishtala’s writeback request is a request to
transfer a data block out of the cache memory, not to store the data block in
cache memory and any status returned in response to such a writeback
request would not be “a status indicating that . . . [a] data block has been
stored in the cache memory,” as recited in claim 1 (emphasis added).
Accordingly, the Examiner has not persuasively established that
Nishtala teaches or suggests the disputed limitation, and has not articulated a
prima facie case for obviousness of claim 1. Appellants have, therefore,
persuaded us of Examiner error and we will not sustain the rejection of claim
1, and, for the reasons set forth supra, claims 2-17, 19-21, and 23-25.

ORDER
The decision of the Examiner to reject claims 1-17, 19-21, and 23-25
under 35 U.S.C. § 103(a) as unpatentable over Stenfort and Nishtala is
reversed.

REVERSED

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