Ex Parte Ogawa et al

Patent Trial and Appeal Board

Jan 29, 2018

14568446 (P.T.A.B. Jan. 29, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/568,446 12/12/2014 Kazuto OGAWA 36856.3174 8714
54066 7590 01/31/2018
MURATA MANUFACTURING COMPANY, LTD.
C/O KEATING & BENNETT, LLP
1800 Alexander Bell Drive
SUITE 200
Reston, VA 20191
EXAMINER
VARGHESE, ROSHN K
ART UNIT PAPER NUMBER
2847
NOTIFICATION DATE DELIVERY MODE
01/31/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
JKEATING@KBIPLAW.COM
u spto @ kbiplaw. com
cbennett @ kbiplaw. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KAZUTO OGAWA and ISAO KATO
(Applicants: Murata Manufacturing Co., Ltd.)
Appeal 2017-002628
Application 14/568,446
Technology Center 2800
Before MICHAEL P. COLAIANNI, JAMES C. HOUSEL, and
CHRISTOPHER L. OGDEN, Administrative Patent Judges.
COLAIANNI, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2017-002628
Application 14/568,446
Appellants appeal under 35 U.S.C. § 134(a) the final rejection of
claims 2—4, 7, 10-16, and 18-21. Claim 5 is objected to as depending from
a rejected base claim (Final Act. 2). The Examiner indicates that claim 5
would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims. Id. We have
jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b).
We REVERSE.
The appeal is directed to an electronic component unit having a
component mounted on a substrate and to a manufacturing method for the
electronic component (Spec. ^ 1).
Claim 2 is illustrative:
2. An electronic component unit comprising:
an interposer substrate including principal surfaces opposing each
other and side surfaces between the principal surfaces; and
only one chip capacitor mounted on one of the principal surfaces of
the interposer substrate; wherein
the side surfaces of the interposer substrate include a first side surface
formed before the only one chip capacitor is mounted on the substrate and a
second side surface formed after the only one chip capacitor is mounted on
the interposer substrate;
as viewed from a line normal to the principal surfaces of the
interposer substrate, a distance between the first side surface and the only
one chip capacitor is different from a distance between the second side
surface and the only one chip capacitor; and
as viewed from the line normal to the principal surfaces of the
interposer substrate, the only one chip capacitor extends beyond the first side
surface and extends to outside of the interposer substrate.
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Appeal 2017-002628
Application 14/568,446
Appellants appeal the following rejections:
1. Claims 2—4, 7, and 19-21 are rejected under 35 U.S.C. § 103(a) as
obvious over Sato (JP 2004-335657 A; published Nov. 25, 2004) in
view of Corisis (US 2004/0150088 Al; published Aug. 5, 2004).
2. Claims 10-16 and 18 are rejected under 35 U.S.C. § 103(a) as obvious
over Sato in view of Corisis and Katsumata (JP HI 1168149 A;
published June 22, 1999).
FINDINGS OF FACT & ANALYSIS
The Examiner finds that Sato teaches all the limitations of claim 2
except that Sato does not explicitly teach the chip is a chip capacitor and the
limitation that requires that as the electronic device is viewed from a line
normal to the principal surfaces of the interposer substrate, the only one chip
capacitor extends beyond the first side surface and extends to outside of the
interposer substrate (Final Act. 3). The Examiner finds that Sato discloses
that the chip may be a chip capacitor (Final Act. 3). The Examiner
concludes that it would have been obvious to use a chip capacitor as the chip
as taught by Sato and to increase the stability of a circuit (Final Act. 4).
Regarding the extension of the chip capacitor beyond the first side
surface of the interposer substrate, the Examiner finds that Corisis teaches
extending the chip capacitor beyond the first side surface to outside the
interposer substrate (Final Act. 4). The Examiner concludes that it would
have been obvious to have the chip capacitor extend beyond the first surface
and outside of the interposer substrate as taught by Corisis in order to
increase the capacity for external contacts while maintaining the size of the
assembly and package as taught by Corisis (Final Act. 5).
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Appeal 2017-002628
Application 14/568,446
Appellants argue that the Examiner has not provided any reason or
motivation to modify the unit of Sato so as to include the extension of the
chip capacitor beyond the first side surface of the interposer substrate as
viewed from a position normal to the interposer substrate (App. Br. 7-8).
Appellants contend that in the Examiner’s annotated Figure 2 of Sato, the
chip capacitor 10 would have to extend beyond the “first side surface” of the
interposer substrate 30 in the widthwise direction (App. Br. 8). Appellants
contend that Corisis teaches that the die 12 extends beyond the interposer
substrate 14 in the lengthwise direction, not the widthwise direction (App.
Br. 9). Appellants contend that Corisis teaches in paragraph 31 that the die
12 must not be wider than the substrate 14 (App. Br. 9). Appellants argue
that Corisis’ paragraph 34 relied upon by the Examiner does not support the
Examiner’s finding that the modification would increase the capacity for
external contacts while maintaining the size of extension of the interposer
substrate (App. Br. 9). Appellants maintain that paragraph 34 of Corisis
teaches that the extension of the interposer substrate and not the die (i.e., the
chip) increases the number of contacts (App. Br. 9). Appellants argue that
Corisis teaches away from making the die 12 wider than the interposer
substrate 14 (App. Br. 9-10). Appellants contend that Sato in Figure 2
already teaches making the interposer substrate wider than the die as taught
by Corisis so that there is no reason to modify Sato (App. Br. 10).
The Examiner responds that claim 2 does not specify lengths or
widths of the interposer substrate or the chip capacitor so Appellants’
arguments regarding the width or length are not germane to the claims (Ans.
3—4). The Examiner finds that Corisis teaches the concept of having one
side surface of the chip component (12') extending beyond the side surface
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Appeal 2017-002628
Application 14/568,446
of the substrate 14' (Ans. 4). The Examiner finds that Sato teaches a
conventional packaging as taught by Corisis where the package is longer at
portions of the sides than the chip component in both X and Y directions
(Ans. 8).
Appellants argue that unlike Corisis that uses a ball grid array (BGA)
to allow multiple connections to semiconductor die, Sato is directed to a chip
capacitor mounting that has only two electrodes 11 (Reply Br. 3-4).
Appellants contend that Sato is not a conventional BGA as Corisis (Reply
Br. 4). Appellants contend that Sato’s chip capacitor would require only two
electrode connections such that there would have been no motivation for an
increased capacity of the electrodes 11 (Reply Br. 4).
The preponderance of the evidence favors Appellants’ argument of
nonobviousness. Although the Examiner is correct that the claim does not
specify a width or a length direction, the applied prior art (Corisis) does
specify that the interposer substrate (14 or 14') is wider than the
semiconductor die 12 or 12' (Corisis 8, 9). Corisis explains that by
having the width of the support substrate 14 or 14’ greater than the
semiconductor die 12 or 12' provides a greater surface area for supporting
external contacts (]| 34). In other words, Corisis teaches to make the
interposer wider than the chip it supports. This finding is important because
the Examiner’s combination of Sato and Corisis is based upon modifying the
Examiner’s annotated Figure 2 of Sato so that the chip 10 extends past what
the Examiner has labelled “1st SIDE SURFACE” in the annotated Figure.
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Appeal 2017-002628
Application 14/568,446
The Examiner’s annotated Figure 2 of Sato is shown below:
I DISTANCE A |
I I
-ivXXxx:: xXxxX.......-
* I
I 1st SIDE I
j SURFACE |
'"""”A"... "
41 V 41 /
x iV,v^.jw^vsc*? r 'V "....................................f
/w. % s. <\v ^ ..............................................................j...................;;.................t............
-—10
TF
j DISTANCES ‘“'“i i s *
31
2nd S^D€
1 SURFACE 1
,x ,^«S5fi5
t.yj
. i ,{m^X }
' '} yV
j##*
i :>
— 31
-30
41 41
Annotated Drawing 2 from Sato (JP 2004-335657A)
Examiner’s annotated Figure 2 of Sato.
Based upon Corisis’ teachings, the substrate support 30 in Sato would be
extended in the width direction so that it is made wider than the chip 10. So
the first side surface of the substrate support 14 as identified by the
Examiner would have been extended rather than the width of the chip 10 as
taught by Corisis. In other words, although the claims do not specify a
width or length orientation, the applied prior art is specifying how the
modification would have taken place. Appellants’ arguments are directed to
whether the applied prior art teachings would have suggested the claimed
subject matter.
The Examiner in the Answer finds that Corisis teaches that the die
preferably extends beyond the interposers in the lengthwise direction (Ans.
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Appeal 2017-002628
Application 14/568,446
8). The Examiner does not change Sato’s annotated Figure 2 in addressing
Appellants’ arguments in the Answer (Ans. 7). Presumably the Examiner
finds that length and width may be arbitrarily assigned and the portion of the
substrate support 30 labelled “1st SIDE SURFACE” in the annotated figure
may be considered the end of the length of the substrate support. Length is
defined as “the longer or longest dimension of an object.”1 Accordingly, the
relative longest dimension shown in Sato’s Figure extends along what the
Examiner labels “1st SIDE SURFACE.” With this understanding in mind,
the extension of Sato’s chip 10 would occur past what the Examiner has
labelled as “2nd SIDE SURFACE” in Sato’s annotated Figure 2. This
extension would comport with what Corisis teaches in terms of how the chip
12 is to extend (Corisis Fig. 4). But the benefit achieved by Corisis in terms
of having greater surface area for external contacts in a ball grid array
involves expanding the width of the substrate support 30 so that it is wider
than the chip 10. The Examiner has not explained sufficiently why one of
ordinary skill in the art would have combined Corisis’ teachings directed to
increasing connections in a ball grid array for a semiconductor die (i.e., an
integrated circuit) with Sato chip capacitor that only uses two terminals so
that the chip 10 is wider than the substrate support 30 (Corisis ^ 34; Sato ^
36). The Examiner has not explained why Corisis’ teaching the concept of
having a chip overhang the edge of a substrate support in the lengthwise
direction would have led to increasing the capacity for external contacts
while maintaining the size of the assembly and package (Final Act. 5; Ans.
4).
i https://www.merriam-webster.com/dictionary/length, accessed January 16, 2018.
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Appeal 2017-002628
Application 14/568,446
On this record, we reverse the Examiner’s § 103 rejection over Sato in
view of Corisis. In the Examiner’s § 103 rejection over Sato in view of
Corisis and Katsumata, the Examiner relies on the same faulty combination
of Sato and Corisis (Final Act. 10-14). We reverse the Examiner’s § 103
rejection over Sato in view of Corisis and Katsumata.
DECISION
The Examiner’s decision is reversed.
ORDER
REVERSED
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