Ex Parte Norman

Patent Trial and Appeal Board

Oct 30, 2014

12069105 (P.T.A.B. Oct. 30, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE
THE PATENT TRIAL AND APPEAL BOARD
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Ex parte Robert Norman1
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Appeal 2012-009971
Application 12/069,105
Technology Center 2100
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Before BEVERLY A. FRANKLIN, LINDA M. GAUDETTE, and
MARK NAGUMO, Administrative Patent Judges.

NAGUMO, Administrative Patent Judge.

DECISION ON APPEAL
Robert Norman (“Norman”) timely appeals under 35 U.S.C. § 134(a)
from the Final Rejection2 of claims 1–27, which are all of the pending
claims. We have jurisdiction. 35 U.S.C. § 6. We reverse.

1 The real party in interest is listed as Unity Semiconductor Corporation.
(Appeal Brief, filed 14 October 2011 (“Br.”), 2.)
2 Office action mailed 13 July 2011 (“Final Rejection”; cited as “FR”).
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OPINION
A. Introduction3
The subject matter on appeal relates to memory access control circuits
for controlling access to multiple layers of memory in third dimension
memory technology.4 (Spec. 1 [0002].) In one aspect, the claimed circuits
and methods are said to provide efficient write-protection methods to ensure
the integrity of executable instructions or data files stored in memory.
(Id. at [0003].) In another aspect, by using some of the cells in the memory
layers of the third dimension memory for access control memory, rather than
adding memory to the logic layer, the die size of the logic layer need not be
increased. (Id. at 8–9 [0022].)
Claim 1 is representative of the dispositive issues and reads:
A memory access control circuit, comprising:
[a] a silicon semiconductor substrate including a logic
layer,
the logic layer including circuitry fabricated on the
silicon semiconductor substrate;
[b] a third dimension memory
in direct contact with and fabricated directly above the
silicon semiconductor substrate and

3 Application 12/069,105, Integrated circuits and methods to control access
to multiple layers of memory, filed 7 February 2008. We refer to the
“ʼ105 Specification,” which we cite as “Spec.”
4 A particular technological embodiment of third dimension memory is
described in application 11/095,026, filed 30 March 2005, which Norman
identifies as a related case, with assigned appeal number 2011-001562.
(Br. 2.) We affirmed the appealed rejections in that case in an Opinion
dated 20 November 2013; that application was abandoned
on 12 February 2014.
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electrically coupled with at least a portion of the
circuitry;
[c] a memory access circuit included in the circuitry, the
memory access circuit including
[1] a permissions list repository configured to store
access control data in the third dimension memory for
an address; and
[d] an access detector included in the circuitry,
the access detector responsive to the access control data,
the access detector configured to detect the address for
accessing a memory location in the third dimension
memory and
configured to generate an access disable signal
configured to disable access to the memory location.
(Claims App., Br. 17; some indentation, paragraphing, square-bracketed
labelling, and emphasis added.)
Independent claim 14 (also drawn to a memory access control circuit)
contains a requirement similar to requirement [c][1], namely, “the third
dimension memory including an access control memory including subsets of
third dimension memory cells configured to store portions of a permissions
list.” (Claims App., Br. 19.) Independent claim 20 (drawn to a method for
controlling access operations to a third dimension memory) contains the
corresponding requirements of
detecting an access operation in relation to a first memory
location in a first plane of memory in multiple layers of third
dimension memory; and
accessing a second memory location in a second plane of
memory in the multiple layers of third dimension memory to
determine whether to restrict the access operation.
(Claims App., Br. 20; indentation added.)
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The Examiner maintains the following grounds of rejection:5
A. Claims 1–5, 7–18, and 20–27 stand rejected under
35 U.S.C. § 103(a) in view of the combined teachings of
Taussig6 and Mendell.7
A1. Claims 6 and 19 stand rejected under 35 U.S.C. § 103(a) in
view of the combined teachings of Taussig, Mendell, and
Junya.8
B. Discussion
Findings of fact throughout this Opinion are supported by a
preponderance of the evidence of record.
Initially, we find that Norman has raised arguments for the
patentability of each independent claim, but not for any of the dependent
claims, including separately rejected claims 6 and 19. Moreover, Norman
has raised an argument with respect to the common limitation [c][1]
highlighted supra. In the event, all claims stand or fall with claim 1.9

5 Examiner’s Answer mailed 7 December 2011 (“Ans.”).
6 Carl P. Taussig and Richard E. Elder, Defect management enabled PIRM
and method, U.S. Patent No. 7,106,639 B2 (2006).
7 Harry B. Mendell, Memory management arrangement for microprocessor
systems, U.S. Patent No. 4,519,032 (1985).
8 Tempaku Junya, U.S. Patent No. 5,469,564 (1995).
9 Following the Examiner’s Answer, Norman filed on 7 March 2012,
a paper styled “Amendment & Reply per 37 C.F.R. §1.111 to Re-Open
Prosecution,” in which claims 3–10 and 14–27 were canceled, sole
remaining independent claim 1 was amended substantially, and the
remaining claims amended to comport with amended claim 1. This paper
was denied entry as improper under 37 C.F.R. § 41.33(b) and (c), as well as
improper under 37 C.F.R. § 1.111. (Notice mailed 26 March 2012.)
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Briefly, the Examiner finds that Taussig describes a third dimension
memory including limitations [a] and [b], but not [c] and [d]. (FR 3–5.) The
Examiner finds that Mendell describes the permissions list repository
configured to store access control data in the third dimension memory
required by limitation [c] at column 2, lines 3–18, and the access detector
required by limitation [d] at column 2, lines 30–48. (Id. at 8.)
Norman argues that neither Taussig nor Mendell discloses third
dimension memory. (Br., para. bridging 11–12; and 13, 1st full para.) More
particularly, Norman urges that “Mendell does not describe, disclose,
motivate or suggest . . . or the third dimension memory including an access
control memory including subsets of third dimension memory cells
configured to store portions of a permissions list.” (Id. at 13, ll. 14–19;
emphasis added.)
In the words of the ʼ105 Specification, “[a] memory is a ‘third
dimension memory’ (or a third dimensional memory) when it is fabricated
above other circuitry components, the components usually including a
silicon substrate, polysilicon layers and, typically, metallization layers.”
(Spec. 10 [0025].) Norman has not explained why the layered memory
described by Taussig would not have been regarded by persons having
ordinary skill in the art as not meeting this general definition. Moreover, as
the Examiner points out (“Taussig states ‘Although shown on the top
layer 110, the controller 106 may be provided on any layer as dictated by
fabrication or other preferences.’” (Ans. 18, ll. 6–8, emphasis omitted,
quoting Taussig, col. 5, ll. 33–35.) Given the broad disclosure and broad
definitions in the Specification, we are not persuaded of harmful error in the
Examiner’s findings that Taussig teaches a “third dimension memory” or a
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logic layer, or the position of the logic layer. We neither express nor imply
any findings or opinions regarding claims not presented for appeal.
Mendell describes, at column 2, lines 3–18, memory management via
twelve memory maps, each defining a memory space. Five are allowed to
be accessed when the memory management flag is set to user mode, and the
contents of the memory maps are said to be “only accessible when the
memory management flag is set to the kernel mode.” (Mendell, col. 2,
ll. 14–15.) The Examiner has not directed our attention to disclosure in this
passage that teaches where the memory maps are stored. Nor has the
Examiner explained why it would have been obvious from these teachings to
store the memory maps in the third dimension memory the Examiner finds
disclosed by Taussig. Obviousness is a conclusion of law based on
underlying facts, and the underlying facts must be supported by evidence.
As our reviewing court has explained, “[e]ven were it obvious to a
practitioner of the art [that a certain consequence would occur], applicants
have the burden to provide the PTO with evidence showing that such is the
case.” In re Mayne, 104 F.3d 1339, 1344 (Fed. Cir. 1997). The same
burden must be carried by the USPTO when an appellant challenges with
reasonable specificity findings of fact.
While it may be reasonable to find that the memory maps described
by Mendell are (or suggest) a “permissions list repository”—a proposition
that, in the present posture of this appeal we may assume without deciding—
we are unable to discern in the passages of Mendell cited by the Examiner a
reasonably specific teaching or suggestion that the map or list repository be
stored in a portion of the memory where the data of interest are stored.
Moreover, the Examiner has found that Taussig is silent on this point.
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We conclude that the Examiner has failed to come forward with
evidence sufficient to support the obviousness of a limitation present in each
of the independent claims.
None of the findings related to the rejections of the dependent claims
cures this defect. We therefore reverse all the appealed rejections.
C. Order
We reverse the rejections of claims 1–27.
REVERSED

cdc