Ex Parte Nogami et al

Patent Trial and Appeal Board

Apr 11, 2013

11210586 (P.T.A.B. Apr. 11, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/210,586 08/24/2005 Takeshi Nogami 50U7072.01 4973
51518 7590 04/11/2013
MAYER & WILLIAMS PC
251 NORTH AVE. WEST
2ND FLOOR
WESTFIELD, NJ 07090
EXAMINER
KING, DOUGLAS
ART UNIT PAPER NUMBER
2824
MAIL DATE DELIVERY MODE
04/11/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_____________

Ex parte TAKESHI NOGAMI and MASANAGA FUKASAWA
_____________

Appeal 2010-009339
Application 11/210,586
Technology Center 2800
______________

Before ROBERT E. NAPPI, DEBRA K. STEPHENS, and
BRIAN F. MOORE, Administrative Patent Judges.

Per Curiam

DECISION ON APPEAL
Appeal 2010-009339
Application 11/210,586

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This is a decision on appeal under 35 U.S.C. § 134(a) of the final
rejection of claims 5, 7, 8, and 10 through 14. Claims 6 and 9 have been
canceled claims 1 through 4 have been withdrawn.
We affirm- in-part.
INVENTION
The invention is directed to an arrangement of semiconductor chips
connected through a carbon nanotube conductor formed in a via. See pages
2, 3, and Figure 2C of Appellants’ Specification. Claim 5 is representative
of the invention and reproduced below:
5. A method for interconnecting a plurality of
semiconductor chips, comprising:
forming at least one via through the thickness of at least a
first one of the semiconductor chips;
vertically stacking the first semiconductor chip over a
second semiconductor chip such
that a bottom of the via is exposed to a conductive interconnect
region of the second semiconductor chip;
forming a catalyst layer at the bottom of the via, said
catalyst layer being electrically interconnected to a conductive
interconnect region of the second semiconductor chip;
filling the via with a carbon nanotube conductor;
forming a contact metal pad on a top surface of the carbon
nanotube conductor, said contact metal pad thermally isolated
from a conductive interconnect region of the first
semiconductor chip;
annealing an interface defined by the top surface of the
carbon nanotube conductor and the contact metal pad; and
wiring the contact metal pad and the conductive
interconnect region of the first semiconductor chip after said
annealing step.

Appeal 2010-009339
Application 11/210,586

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REJECTIONS AT ISSUE
The Examiner has rejected claim 5, 10 and 11 under 35 U.S.C.
§ 103(a) as being unpatentable over Ozguz (U.S. 2004/0113222 A1; Jun. 17,
2004), Li (US 7,094,679 B1; Aug. 22, 2006) and Dangelo (U.S.
2004/0152240 A1; Aug. 5, 2004). Answer 3-51.
The Examiner has rejected claims 7, 8, and 14 under 35 U.S.C.
§ 103(a) as unpatentable over Ozguz, Li, Dangelo and Yamazaki (US
2003/0171837 A1; Sep. 11, 2003). Answer 5-6.
The Examiner has rejected claims 12 and 13 under 35 U.S.C. § 103(a)
as unpatentable over Ozguz, Li, Dangelo and Kajiwara (US 1003/0102797
A1; Jun. 5, 2003).

ISSUES
Appellants argue on pages 5 through 9 of the Appeal Brief that the
Examiner’s rejection of claims 5, 7, 8, 10, 11 and 14 is in error.2 These
arguments present us with the issues:
a) Did the Examiner err in finding that the skilled artisan would
combine Ozguz and Dangelo such that there would be a contact
metal pad on a top surface of the carbon nano-tube conductor as
recited in representative claim 5?
b) Did the Examiner err in finding that the combination of Ozguz, Li,
Dangelo teaches wiring the contact metal pad and the interconnect

1 Throughout this opinion we refer to the Examiner’s Answer mailed on
March 16, 2010.
2 Throughout this opinion we refer to Appellants’ Appeal Brief filed on
December 22, 2009.
Appeal 2010-009339
Application 11/210,586

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region of the semiconductor chip after an annealing step as recited
in representative claim 5?

Further, Appellants present separate arguments with respect to the
rejection of claim 13 on pages 9 and 10 of the Appeal Brief which presents
us with the additional issue:
c) Did the Examiner err in finding the combination of Ozguz, Li,
Dangelo and Kajiwara teach using an oxygen plasma process to
form a recess in a top surface of the nanotube material?

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
contentions that the Examiner has erred. Further, we have reviewed the
Examiner’s response to Appellants’ arguments.
We disagree with Appellants’ conclusion that the Examiner erred in
finding an oridnarily skilled artisan would combine Ozguz and Dangelo such
that there would be a contact metal pad on a top surface of the carbon-nano
tube conductor and the combination of Ozguz, Li, Dangelo teaches wiring
the contact metal pad and the interconnect region of the semiconductor chip
after an annealing (Issues a and b). However, we agree with the Appellants
that the Examiner erred in finding the combination of Ozguz, Li, Dangelo
and Kajiwara teach using an oxygen plasma process to form a recess in a top
surface of the nano-tube material (Issue c).
With respect to the first two issues the Examiner has provided a
comprehensive explanation of how the each of the reference teach the
claimed steps and how a skilled artisan would combine these teachings on
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Application 11/210,586

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pages 8 through 14 of the Answer. Further, the Examiner, on pages 15 and
16 of the Answer has provided a well-reasoned response to the issues raised
by Appellants. We have reviewed and concur with the Examiner’s fact
finding and conclusions with respect to representative claim 5. Accordingly,
we sustain the Examiner’s rejections of claims 5, 7, 8, 10, 11, 12 and 14. 3
With respect to the third issue, the Examiner responds to Appellants’
arguments by finding that the claimed recess is not limited to the recess as
shown in a drawing on page 17 of the Answer but instead is broad enough to
encompass a situation as shown in a drawing on page 18 of the Answer. We
disagree with the Examiner’s claim interpretation as the Examiner has not
shown the interpretation is consistent with Appellants’ Specification and we
do not consider the drawing on page 18 of the Answer to show a recess in a
top surface as recited. We note that Appellants’ Figure 2A and 2B both show
that the metal pad (item 207) is in a recess in chip (item 2021) and the
surface of nanotube material (item 210). Accordingly, we will not sustain
the Examiner’s rejection of claim 13.
DECISION
The decision of the Examiner to reject claims 5, 7, 8, and 10 through
14 is affirmed-in-part.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

3 We note that though Appellants grouped claim 12 with the discussion of
claim 13, the limitation argued with respect to claim 13 is not present in
claim 12, therefore we consider Appellants’ arguments directed to claim 5 to
be the only arguments applicable to claim 12.
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AFFIRMED-IN-PART

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