Ex Parte Nancekievill et al

Patent Trial and Appeal Board

Mar 25, 2013

11157343 (P.T.A.B. Mar. 25, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte DOMINIC NANCEKIEVILL and PAUL METZGEN
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Appeal 2010-010156
Application 11/157,343
Technology Center 2100
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Before DEBRA K. STEPHENS, LYNNE E. PETTIGREW, and BARBARA
A. PARVIS, Administrative Patent Judges.

STEPHENS, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2010-010156
Application 11/157,343

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Appellants appeal under 35 U.S.C. § 134(a) (2002) from a final
rejection of claims 12, 14, 16-19, and 23-29. We have jurisdiction under 35
U.S.C. § 6(b). Claims 1-11, 13, 15, 20-22, and 30 have been cancelled.
We AFFIRM.

Introduction
According to Appellants, the invention relates to adder units used to
compare two numbers. (Abstract).

STATEMENT OF THE CASE

Exemplary Claim
Claim 12 is an exemplary claim and is reproduced below:
12. Comparator circuitry for use in comparing at least two
numbers, the comparator circuitry comprising:

a first look-up table circuit having a first
input for receiving a first bit from a first number, a second
input for receiving a second bit from the first number, and a third
input for receiving a first bit from a second number, the first look-up
table being configured to produce a first output having a logic value
that is (a) NOT the second bit from the first number when the first bit
from the first number and the first bit from the second number are
equal, (b) 1 if the first bit from the first number is less than the first bit
from the second number, and (c) 0 if the first bit from the first number
is greater than the first bit from the second number;

a second look-up table circuit having a fourth input for receiving
the first bit from the second number, a fifth input for receiving a
second bit from the second number, and a sixth input for receiving the
first bit from the first number, the second look-up table being
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configured to produce a second output having a logic value that is (a)
the second bit from the second number when the first bit from the first
number and the first bit from the second number are equal, (b) 1 if the
first bit from the first number is less than the first bit from the second
number, and (c) 0 if the first bit from the first number is greater than
the first bit from the second number; and

an adder circuit for adding the first and second outputs.

References
Hokenek US 2003/0172102 A1 Sep. 11, 2003
Leijten-Nowak (“L-N”) US 7,251,672 B2 Jul. 31, 2007
Jan Tai, New Stratix II Devices Now Supported by Synplify® Software,
Synplicity Inc. Vol. 4, Issue 1, 2004, (“Synplicity”)

Rejections
(1) Claims 12, 14, 16-19, and 23-27 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Synplicity and L-N.
(2) Claims 28 and 29 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Synplicity, L-N, and Hokenek.

GROUPING OF CLAIMS

Based upon Appellants’ arguments, we select representative claim 12
to decide this appeal for the group consisting of claims 12, 14, 16-19, and
23-27. (See App. Br. 9-12).
Based upon Appellants’ arguments, we address the rejection of claims
28 and 29 separately. (See App. Br. 12).
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We have only considered those arguments that Appellants actually
raised in the Briefs. Arguments Appellants could have made but chose not
to make in the Briefs have not been considered and are deemed to be
waived. See 37 C.F.R. § 41.37(c)(1)(vii)(2011).

ISSUE 1
35 U.S.C. § 103(a): claims 12, 14, 16-19, and 23-27
Appellants assert their invention is not obvious over Synplicity and L-
N (App. Br. 9-11). Specifically, Appellants contend neither Synplicity nor
L-N, taken alone or in combination, discusses anything about comparing two
numbers (App. Br. 9). According to Appellants, Synplicity does not suggest
a shared input should be one bit from one of two numbers being compared,
while another such shared input is one bit from the other of those numbers
(App. Br. 9-10). Nor does Synplicity disclose or suggest that other inputs to
those look-up tables should be respective second bits from each of the two
numbers being compared (App. Br. 10). Appellants further insist Synplicity
does not disclose two different configurations for each of two look-up tables
and applying the outputs of those two look-up tables to an adder (App. Br.
10-11). Thus, according to Appellants the invention cannot properly be said
to be obvious in light of Synplicity (id.).

Issue 1a: Has the Examiner erred in finding the combination of
Synplicity and L-N teaches or suggests “[c]omparator circuitry for use in
comparing at least two numbers” as recited in claim 12?
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Issue 1b: Did the Examiner use improper hindsight reconstruction?

ANALYSIS
We agree with the Examiner’s findings and conclusion and adopt
them as our own. Initially we note the claims as recited do not prohibit use
of other bits in the numbers for input to the look-up table circuitry.
Moreover, we disagree with Appellants that the references do not show
performing a comparison (see e.g., Synplicity, pg. 3, ¶2).
We further emphasize an ordinarily skilled artisan would have
recognized the recited look-up table circuit “is a basic logic operation in a
digital circuit” as maintained by the Examiner (Ans. 10). We further agree
with the Examiner that a person of ordinary skill would use a look-up table
as disclosed by Synplicity to perform a logic function such as a comparison
(Ans. 10-12). In addition, we agree with the Examiner that L-N teaches a
programmable device (with a look-up table) that can be configured to
produce any desired output for input bit combinations and that an ordinarily
skilled artisan could pick a desired combination based on design choice
(Ans. 14-15). Both Synplicity and L-N teach use of a look-up table and
logic devices to perform logic functions (Synplicity, pg. 1; L-N, col. 1, ll. 3-
21). Indeed, Appellants have not persuaded us picking a desired
combination of input bits or using two different look-up table circuitry as
recited was more than a design choice or was uniquely challenging or
otherwise beyond the level of ordinarily skilled artisans.
And thus it follows we are not persuaded the Examiner used
impermissible hindsight in combining the teachings and suggestions of
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Synplicity and L-N to achieve the present invention. Accordingly, the
Examiner did not err in finding the combination of Synplicity and L-N
teaches or suggests the invention as recited in claim 12 and dependent
claims 14, 16-19, and 23-27, not separately argued. Therefore, the Examiner
did not err in rejecting claims 12, 14, 16-19, and 23-27 under
35 U.S.C. § 103(a) for obviousness over Synplicity and L-N.

ISSUE 2
35 U.S.C. § 103(a): claims 28 and 29
Appellants do not separately argue the rejection of claims 28 and 29,
but instead rely on the arguments set forth for claim 12. Accordingly, based
on the reasons set forth above with respect to claim 12, we are not persuaded
the Examiner did not err in finding the combination of Synplicity, L-N, and
Hokenek teaches or suggests the invention as recited in claims 28 and 29.
Therefore, the Examiner did not err in rejecting claims 28 and 29 under
35 U.S.C. § 103(a) for obviousness over Synplicity, L-N, and Hokenek.

DECISION
The Examiner’s rejection of claims 12, 14, 16-19, and 23-27 under
35 U.S.C. § 103(a) as being unpatentable over Synplicity and L-N is
affirmed.
The Examiner’s rejection of claims 28 and 29 under
35 U.S.C. § 103(a) as being unpatentable over Synplicity, L-N, and Hokenek
is affirmed.
Appeal 2010-010156
Application 11/157,343

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2011).

AFFIRMED

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