Ex Parte Nakao

Patent Trial and Appeal Board

Nov 26, 2014

10609603 (P.T.A.B. Nov. 26, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte TOMOAKI NAKAO
____________________

Appeal 2012-0081081
Application 10/609,603
Technology Center 2600
____________________

Before JEAN R. HOMERE, CARL W. WHITEHEAD JR., and JEFFREY S.
SMITH, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 2, 7, 24, 25, and 30. Claims 1, 3–6, 8–23, and 26–29
have been withdrawn. App. Br. 2–3. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.

1 The real party in interest is Sharp Kabushiki Kaisha. App. Br. 1.

Appeal 2012-008108
Application 10/609,603

2
Appellant’s Invention
Appellant invented a synthesizing circuit (4) for synchronizing a clock
signal (CK) and a data signal received at a sending logic circuit (2) to
transmit the two received signals as a single multilevel signal to a receiving
logic circuit (3). Spec. 18:8–17, Fig. 1.
Illustrative Claim
Independent claim 2 further illustrates the invention as follows:

2. A logic circuit for transmitting one clock signal and at
least one logic data signal in sync with said one clock signal to
another logic circuit, comprising:
at least one synthesizing section configured to synthesize
said one clock signal with said at least one logic data signal to
produce one multivalued logic signal and transmit the
multivalued logic signal to the another logic circuit,
wherein the multivalued logic signal has at least three
different logic levels, and each of the different logic levels has a
different signal strength,
wherein the at least one synthesizing section includes a
plurality of sources and a plurality of switches provided
between the plurality of sources and an output section, each of
the plurality of sources generates a different signal strength,
wherein the plurality of switches are controlled in
response to the at least one logic data signal and the one clock
signal,
wherein the plurality of switches include a first switch
and a second switch that are connected to the output section in
such a manner that the first switch and the second switch are in
parallel and turn off or on in response to the one clock signal,
and the plurality of switches also include a third switch and a
fourth switch that are directly connected to only an input of the
second switch in such a manner that the third switch and the
Appeal 2012-008108
Application 10/609,603

3
fourth switch are in parallel and tum off or on in response to the
at least one logic data signal.

Prior Art Relied Upon
The Examiner relies on the following prior art as evidence of
unpatentability:
Muramatsu US 4,215,418 July 29, 1980
Lee US 5,801,548 Sept, 1, 1998
Knotz US 6,289,055 B1 Sept. 11, 2001
Brewer US 6,456,159 B1 Sept, 24, 2002

Rejections on Appeal
The Examiner rejects claims 2, 7, 24, 25, and 30 as follows:
1. Claims 2, 7, 24, 25, and 30 stand rejected under 35 U.S.C. § 112, first
paragraph, as failing to comply with the written description
requirement.
2. Claims 2, 7, 24, 25, and 30 stand rejected under 35 U.S.C. § 112, first
paragraph, as failing to comply with the enablement requirement.
3. Claims 2, 7, 24, 25, and 30 stand rejected under 35 U.S.C. § 112,
second paragraph, as being indefinite.
4. Claim 2 stands rejected under 35 U.S.C. § 112, second paragraph, as
being incomplete.
5. Claims 2, 7, and 24 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Knotz, Muramatsu, and Lee.
Appeal 2012-008108
Application 10/609,603

4
6. Claims 25 and 30 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Knotz, Muramatsu, Lee, and
Brewer.
ANALYSIS
We consider Appellant’s arguments seriatim as they are presented in
the Appeal Brief, pages 13–47, the Reply Brief, pages 2–13, and the
Supplemental Reply Brief, pages 9–17.
112 Rejections
Dispositive Issue 1: Did the Examiner err in concluding that the
limitation of “a third switch and a fourth switch that are directly connected
to only an input of the second switch,” as recited in claim 2, renders the
claim non-compliant with the written description requirement and the
enablement requirement under 35 U.S.C. § 112, first paragraph? Likewise,
did the Examiner err in concluding that the cited limitation renders the claim
indefinite and incomplete under 35 U.S.C. § 112, second paragraph?
Appellant argues the Examiner erred in concluding that the afore-cited
limitation renders the claim non-compliant with § 112, first paragraph, and §
112, second paragraph. Reply Br. 4. In particular, Appellant argues because
Figure 3, as originally filed, depicts that “the third switch (SW3) and the
fourth switch (SW4) are connected to only an input of the second switch
(SW2) without any intervening components,” one of ordinary skill in the art,
having read the Specification, would have interpreted the limitation as SW3
and SW4 being connected to only one of the inputs of WS2. Id. Therefore,
Appellant submits the Examiner’s interpretation of the disputed limitation as
Appeal 2012-008108
Application 10/609,603

5
SW3 and SW4 having only a single connection to SW2, and no other
components, is not consistent with Appellant’s Specification or the meaning
the ordinarily skilled artisan would have given thereto. Id. at 5–8, App. Br.
15–18.
In response, the Examiner concludes that, except for the depiction
provided in Figure 3, Appellant’s original disclosure of the invention
provides no discussion of the term “directly connected.” Ans. 20.
According to the Examiner, because the term “only” would be commonly
recognized by the ordinarily skilled artisan as “alone, solely, exclusively or
no more than,” the recitation “directly connected to only an input of the
second switch” can be reasonably construed as SW3 and SW4 having no
more than one direct connection (i.e., the connection with SW2), thereby
teaching against the additional direct connections of SW3 and SW4 with
other inputs as depicted in Figure 3. Id. at 20–45, Supp. Ans. 2–9.
We find error in the Examiner’s rejections under 35 U.S.C. § 112,
first paragraph, and § 112, second paragraph. In particular, we find
unreasonable the Examiner’s interpretation of the disputed limitation
because such interpretation is not supported by the record before us. That is,
one of ordinary skill in the art, examining originally filed Figure 3, would
not have construed the disputed limitation to render SW3 and SW4
inoperable, as per the Examiner’s interpretation, when another plausible and
workable interpretation of the disputation limitation is also ascertainable
from the cited Figure. As correctly argued by Appellant, Figure 3 clearly
supports that SW3 and SW4 have a direct connection to only one of the
Appeal 2012-008108
Application 10/609,603

6
plurality of inputs to SW2. The Figure also supports that SW3 has a direct
connection to ½ VDD and to a data source. Likewise, the Figure also
supports that SW4 has a direct connection to GND and a data source. AS
noted by the Examiner, the recitation of SW3 and SW4 being directly
connected to only an input of SW2 can be interpreted as SW3 and SW4
being directly connected to only an input of SW2, and nothing else.
However, as correctly argued by Appellant, such an interpretation would not
be reasonable because it would render SW3 and SW4 inoperable, and would
thereby vitiate the additional claim recitation that SW3 and SW4 turn off or
on in response to a data signal. App. Br. 23–24. Accordingly, we agree
with Appellant that the proper interpretation of the disputed claim limitation
is that SW3 and SW4 are directly connected to only one of the plurality of
inputs to SW2. Therefore, the recited limitation does not preclude SW3 and
SW4 from being also connected to other sources. Because the Examiner’s §
112, first paragraph, and § 112, second paragraph, rejections of the claims
on appeal are premised upon the Examiner’s unreasonable interpretation of
the disputed limitation, we reverse these rejections as set forth above.

Obviousness Rejections
Dispositive Issue 2: Under 35 U.S.C. § 103(a), did the Examiner err
in finding that the combination of Knotz, Muramatsu, and Lee teaches or
suggests a synthesizing section that includes a first switch and a second
switch in parallel so that the switches turn on or off in response to a clock
signal, as well as a third switch and a fourth switch arranged in parallel
Appeal 2012-008108
Application 10/609,603

7
that are directly connected to only an input of the second switch so that the
third switch and the fourth switch turn on or off in response to a logic data
signal, as recited claim 2?
Appellant argues the proposed combination of references does not
teach or suggest the disputed limitations emphasized above. App. Br. 29–
30, Reply Br. 11. According to Appellant, although Knotz discloses a
multivalued logic having three levels, it does not teach the synthesizing
section. Id. at 29–30. Further, Appellant argues while Muramatsu discloses
a plurality of switches in an AND gate that receives two logic levels, it does
not produce a multivalued logic signal. Id. at 31. Likewise, Appellant
argues Lee’s disclosure of a plurality of switches included in an input buffer
to transfer an input signal from a high impedance circuit to a low impedance
circuit does not produce the multivalued signal. Id. Additionally, Appellant
argues incorporating Muramatsu’s AND gate and Lee’s input buffer into
Knotz’ multivalued signal generator would not improve the generator
because the AND gate and the input buffer are directed to different functions
from the synthesizing section. Id., id. at 11.
In response, the Examiner finds that substituting Muramatsu’s AND
gate containing a plurality of switches for Knotz’ AND gate disclosure
would predictably result in a synthesizing circuit containing a plurality of
switches that receive a data signal and a clock signal to produce a single
multivalued signal having three levels. Ans. 47–50, Supp. Ans. 13–14.
On the record before us, we find Appellant has not persuasively
shown error in the Examiner’s findings and ultimate conclusion of
Appeal 2012-008108
Application 10/609,603

8
obviousness. First, we agree with the Examiner that Appellant’s attack of
the references individually (as opposed to the proffered combination) in the
principal Brief is not persuasive. Ans. 50. Second, we find unpersuasive
Appellant’s additional argument that, even if the combination of Knotz,
Muramatsu, and Lee were proper, none of the transistors turns on or off in
response to a clock signal. App. Br. 31, Reply Br. 11. In particular, we find
Appellant failed to address the Examiner’s reliance upon column 7, line 47
through column 7, line 6 of Lee to teach a plurality of switches connected in
parallel such that selected switches can be turned on or off in response to an
input signal. Id. at 14, 55, Supp. Ans. 16. Although the cited portion of Lee
relied upon by the Examiner is quite extensive, and the Examiner has not
explained how such operation is achieved in Lee, we find Appellant’s failure
to specifically address the merits of the cited textual portions has left
unrebutted the Examiner’s finding on this point. Appellant is reminded that
merely reciting the claim limitations and discussing findings other than those
upon which the Examiner relied upon in the rejection is not a responsive
argument. Such a response to the Examiner’s findings is insufficient to
persuade us of Examiner error, as mere attorney arguments and conclusory
statements that are unsupported by factual evidence are entitled to little
probative value. In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997); see
also In re De Blauwe, 736 F.2d 699, 705 (Fed. Cir. 1984); Ex parte Belinne,
No. 2009-004693, 2009 WL 2477843, slip op. at *7–8 (BPAI Aug. 10,
2009) (informative). See also In re Lovin, 652 F.3d 1349, 1357 (Fed. Cir.
2011) (“[W]e hold that the Board reasonably interpreted Rule 41.37 to
Appeal 2012-008108
Application 10/609,603

9
require more substantive arguments in an appeal brief than a mere recitation
of the claim elements and a naked assertion that the corresponding elements
were not found in the prior art.”); cf. In re Baxter Travenol Labs., 952 F.2d
388, 391 (Fed. Cir. 1991) (“It is not the function of this court to examine the
claims in greater detail than argued by an appellant, looking for [patentable]
distinctions over the prior art.”)
Because Appellant’s arguments have not shown otherwise, we thus
find the cumulative weight and the totality of the evidence on this record
reasonably supports the Examiner’s finding that the combined disclosures of
Knotz, Muramatsu, and Lee would have taught or suggested the disputed
limitations.
For at least the aforementioned reasons, we find Appellant has not
sustained the requisite burden on appeal of providing arguments or evidence
persuasive of error in the Examiner’s rejection of representative claim 2. It
therefore follows that Appellant has not shown that the Examiner erred in
finding that the combination of Knotz, Muramatsu, and Lee renders claim 2
unpatentable.
Because Appellant has not presented separate patentability arguments
or has reiterated substantially the same arguments as those previously
discussed for the patentability of claims 2, 7, 24, 25, and 30, they fall
therewith. See 37 C.F.R. § 41.37(c)(1)(vii).

Appeal 2012-008108
Application 10/609,603

10
DECISION
We affirm the Examiner’s obviousness rejections of claims 2, 7, 24,
25, and 30. However, we reverse the Examiner’s § 112, first paragraph, and
§ 112, second paragraph, rejections of claims 2, 7, 24, 25, and 30.
Because we have affirmed at least one ground of rejection with
respect to each claim on appeal, the Examiner’s decision is affirmed. See
37 C.F.R. § 41.50(a)(1).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

hh