Ex Parte Nakanishi et al

Patent Trial and Appeal Board

Mar 28, 2017

13655130 (P.T.A.B. Mar. 28, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/655,130 10/18/2012 Kenichi Nakanishi 880001-5217-US00 6560
134795 7590 03/30/2017
MICHAEL BEST & FRIEDRICH LLP (DC)
100 E WISCONSIN AVENUE
Suite 3300
MILWAUKEE, WI 53202
EXAMINER
KABIR, ENAMUL MD
ART UNIT PAPER NUMBER
2112
NOTIFICATION DATE DELIVERY MODE
03/30/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KENICHINAKANISHI and KEIICHI TSUTSUI
Appeal 2016-005824
Application 13/655,130
Technology Center 2100
Before ELENI MANTIS MERCADER, CARL W. WHITEHEAD JR., and
ADAM J. PYONIN, Administrative Patent Judges.
PER CURIAM.
DECISION ON APPEAL
STATEMENT OF THE CASE
This is a decision on appeal under 35 U.S.C. § 134(a) from the Final
Rejection of claims 9, 10, 12—21, and 23—27, which are all pending claims.
Appeal Brief 4. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.
Introduction
Appellants’ invention relates to a “storage control apparatus
configured to execute storage control on a memory storing an error detection
code along with data.” Specification 1:2-4. Claims 9 and 21 are
independent.
Appeal 2016-005824
Application 13/655,130
Illustrative Claim (Disputed limitations emphasized)
9. A storage control apparatus comprising:
a first error detection block configured to perform a first
error detection after receiving data units from a memory circuit
and after receiving a first error detection code from said memory
circuit, said first error detection code being used during said first
error detection to detect an error in a first one of the data units;
and
a first error detection code generation block configured to
generate said first error detection code, said first error detection
code generation block being configured to write said first error
detection code to said memory circuit along with said first one of
the data units.
Rejections on Appeal1
Claims 9, 10, 12, 14—17, 21, 23, and 25 stand rejected under 35 U.S.C.
§ 102(b) as being anticipated by Hong (US 2009/0055713 Al; February 26,
2009). Final Rejection 2, Advisory Action 2.
Claims 13, 18—20, 24, 26, and 27 stand rejected under 35 U.S.C.
1 Appellants submitted an after-final amendment incorporating the subject
matter of (1) claim 11 into claim 9, and (2) claim 22 into claim 21 (see
Appeal Brief 3), which was entered. However, the Advisory Action
included a new explanation for the rejection of amended claim 9 (and
amended claim 21) which did not correspond to the prior rejection of claim
11. See Advisory Action 2, and Final Rejection 3. Although the prior
anticipation rejection of claim 11 appeared to incorrectly rely on two
references, Appellants did not contest or request a corrected rejection, and
Appellants’ Appeal Brief appears to respond to the new explanation for
amended claim 9. Accordingly, we will consider (1) the new explanation for
the rejection of amended claims 9 and 21 as discussed in the Advisory
Action and the Answer, and (2) the remainder of the Final Rejection, as
comprising the rejection on appeal.
2
Appeal 2016-005824
Application 13/655,130
§ 103(a) as unpatentable over Hong in view of Erez (US 2009/0150747 Al;
June 11, 2009). Final Rejection 8, Advisory Action 2.
ANALYSIS
Rather than reiterate the arguments of Appellants and the Examiner,
we refer to the Final Rejection (mailed August 29, 2014), the Advisory
Action (mailed February 26, 2015), the Appeal Brief (filed July 29, 2015),
the Answer (mailed March 11, 2016), and the Reply Brief (filed May 11,
2016) for the respective details. We have considered in this decision only
arguments Appellants actually raised in the Briefs.
Claim 9
Appellants argue Examiner error because “no disclosure exists
anywhere within Hong regarding the performance of an error detection after
receiving data units from a memory circuit and error detection code from the
memory circuit.” Appeal Brief 14. Appellants contend that
(1) “no ECC data from the memory device 300 of Figure 1 of Hong is
used in the error detection step 412 in Figure 2 of Hong” (Appeal
Brief 14),
(2) “no ECC data from the memory devices 700-730 in Figure 3 of Hong
is used along with original data from the memory devices 700-730 to
perform an error detection” (Appeal Brief 15),
(3) “Figure 3 of Hong fails to disclose, teach, or suggest a first error
detection code generation block configured to write ECC data to a
memory device 700-730 with the data” (Appeal Brief 17), and
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(4) the Advisory Action incorrectly relies on multiple embodiments when
it “refers to the memory devices 300 and 310 in Figure 1 along with
the memory devices 700~730 in Figure 3 in an anticipation rejection.”
Appeal Brief 18.
We are not persuaded by Appellants’ arguments. The Examiner finds,
and we agree, that “Hong teaches at Step 410 (Fig. 2) that normal or original
data are read from the memory along with the ECC data for calculation of
ECC syndrome. This syndrome cannot be calculated without the ECC.”
Answer 3. Appellants do not challenge this finding in the Reply Brief. See
Reply Brief 4—10. The Examiner also correctly finds that Hong teaches that
the “ECC controller 260 is configured to detect and correct errors in data
read from the memory devices 300 and 3102'' Answer 3, (quoting Hong |
57). Appellants’ arguments regarding the Examiner’s citation to multiple
embodiments is not persuasive because the Examiner has relied on Hong’s
teachings as illustrated in Figures 1 and 2, which are directed to the same
subject matter. See Answer 4.
Accordingly, we sustain the Examiner’s rejection of independent
claim 9, and independent claim 21 not separately argued. See Appeal Brief
10.
Claim 10
Appellants argue Examiner error because “Hong fails to disclose that
a memory location in the memory devices 300 and 310 for storing the ECC
data corresponds to a memory location in memory devices 300 and 310 for
storing the data to read from the memory devices 300 and 3102’ Appeal
Brief 22. We are not persuaded by Appellants’ argument. The Examiner
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Appeal 2016-005824
Application 13/655,130
finds, and we agree, that in Hong’s Figure 2, “normal or original data are
read from the memory along with the ECC data” (see Answer 3, as
discussed above regarding claim 9). We further note that in Hong Figure 2,
Step 410 occurs immediately after a single “read operation,” which indicates
both normal data and the ECC data are found at the same memory location
because only one read operation is used to locate both types of data.
Accordingly, we sustain the Examiner’s rejection of dependent claim
10.
Claim 12
Appellants argue Examiner error because the Examiner relies on the
teachings regarding “still further embodiments” in Hong 135 in combination
with teachings regarding “some embodiments” of Figures 1 and 2. Reply
Brief 12—13. We are not persuaded by Appellants’ argument. The
Examiner finds, and we agree, that “[a] buffer is a placeholder for temporary
storage” and “ECC memory 265 is an error correcting buffer” as it stores
data for error detection by ECC block 264. Answer 7, Hong Figure 2; see
also Hong Figure 1.
Here, the claimed “second error detection block” encompasses
Figures 1 and 2 and no reliance on the “still further embodiments” of Hong
135 is necessary. Appellants’ argument that “the Examiner’s Answer fails
to highlight any objective evidence in support of this assertion that a buffer
is a placeholder for temporary storage’ '' (Reply Brief 13) is not persuasive as
Appellants do not challenge the veracity of this statement.
Accordingly, we sustain the Examiner’s rejection of dependent claim
12 and dependent claims 15—17, and 23 not argued separately. See Appeal
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Application 13/655,130
Brief 22. Appellants make essentially the same arguments regarding the
rejection of dependent claims 18, 19, 26, and 27 (see Appeal Brief 27—28)
and we sustain the Examiner’s rejection of dependent claims 18, 19, 26, and
27 by similar reasoning.
Claim 14
Appellants argue Examiner error because “the Examiner’s Answer
fails to highlight any teaching in Hong that would have been sufficient to
show prior knowledge in the art of first error detection not being performed
when the second error detection code is in the error correcting code buffer.”
Reply Brief 13; see also Appeal Brief 23—25. We agree. Although the
Examiner has correctly identified ECC memory 265 as an error correcting
code buffer (see discussion of claim 12 above), claim 14 requires that “said
first error detection block does not perform said first error detection when
said second error detection code is in said error correcting code buffer” and
neither the Final Rejection nor the Answer address the remainder of the
limitation. See Final Rejection 4, Answer 7—8.
Accordingly, we reverse the Examiner’s rejection of dependent claim
14 and dependent claim 25 which recites similar limitations. See Appeal
Brief 23.
Claim 13
Appellants argue Examiner error because claim 13 “provide[s] for a
unit of encoding by the second error detection code [that] is smaller than a
unit of encoding by the first error detection code, which is absent from
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Application 13/655,130
within Erez.” Appeal Brief 27. We are not persuaded of error. The
Examiner finds, and we agree, that Erez teaches:
the memory is operative to store a first set of ECC bits having
information corresponding to a first group of memory cells
having a first size larger than the standard size, and to store a
second set of ECC bits having information corresponding to a
second group of memory cells having a second size smaller than
said first size and being a portion of said first group.
Final Rejection 8, quoting Erez Abstract. Here the Examiner broadly and
reasonably finds the claimed “unit of encoding by the first error detection
code” and “unit of encoding by the second error detection code” encompass
Erez’s first and second group of memory cells. Appellants have not
provided persuasive arguments or technical evidence to rebut the Examiner’s
findings. See, e.g., In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997)
(attorney arguments or conclusory statements are insufficient to rebut a
prima facie case).
Accordingly, we affirm the Examiner’s rejection of dependent claim
13 and dependent claim 24 not argued separately. See Appeal Brief 26.
Claim 20
Appellants argue Examiner error because:
a review of Erez reveals that this reference fails to disclose,
teach, or suggest that error correction algorithm 12 is capable of
performing an error detection after receiving data units from a
the memory array 14 and after receiving an error detection code
from the memory array 14, with error detection code being used
during the error detection to detect an error in a first one of the
data units.
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Application 13/655,130
Appeal Brief 30. We are not persuaded by Appellants’ argument. The
Examiner finds, and we agree, that the claimed “information processing
system” of claim 20 encompasses the combination of Hong’s ECC block and
Erez’s flowchart for a method of writing data circuit configuration. Answer
10, citing Hong || 35, 36; Erez Figure 2,120. Appellants do not challenge
this finding in the Reply Brief. See Reply Brief 15.
Accordingly, we affirm the Examiner’s rejection of dependent claim
20.
DECISION
We affirm the Examiner’s rejection of claims 9, 10, 12, 13, 15—21, 23,
24, 26, and 27.
We reverse the Examiner’s rejection of claims 14 and 25.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). See
37 C.F.R. § 41.50(f).
AFFIRMED-IN-PART
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